report_05-07-2025_03-55-17.html

Report generated on 07-May-2025 at 04:16:01 by pytest-html v3.2.0

Summary

1916 tests ran in 1243.69 seconds.

758 passed, 0 skipped, 1158 failed, 0 errors, 0 expected failures, 0 unexpected passes

Results

Result Test TIDL Subgraphs Complete TIDL Offload Duration Links
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1470] 1 False 18.96
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1470'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1470', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3537849 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.58560s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.58569s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.58572s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.58574s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.58577s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.58586s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.58590s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_758] 1 False 9.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_758'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_758', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537850 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1612] 1 False 9.44
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1612'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1612', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537859 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1775] 1 False 15.73
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1775'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1775', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3537857 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3906s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:55:53.710791069 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_723] 1 False 15.05
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537852 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_759] 1 False 9.10
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_759'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_759', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537862 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5178s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5195s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1533] 1 False 15.18
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1533'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1533', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537861 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_628] 1 False 19.08
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_628'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_628', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3537860 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:55:57.026596959 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1742] 1 False 22.89
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-1' pid=3537863 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9976s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1757] 1 False 18.20
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1757'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1757', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3537865 parent=3536424 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.70930s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.70941s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.70945s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.70947s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.70950s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.70962s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.70968s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1398] 1 False 22.14
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1398'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1398', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3537855 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10584s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.74300s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.74313s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.74318s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.74321s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.74335s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.74366s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.74380s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1030] 1 False 10.26
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1030'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1030', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3537858 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2588s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:55:48.212692820 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1725] 1 False 9.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-1' pid=3537869 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3140s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.31883s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31894s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31898s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31901s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31907s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31930s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31941s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1693] 1 False 9.54
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1693'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1693', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-1' pid=3537856 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:55:47.601481147 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-1: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_893] 1 False 11.73
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_893'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_893', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539019 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6816s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6841s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:55:59.075096488 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1340] 1 False 16.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1340'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1340', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-2' pid=3539020 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3430s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3443s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.325600s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.325645s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.325648s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.325651s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.325658s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.325681s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.325693s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.373161s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.373272s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.373287s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1686] 1 False 13.98
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1686'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1686', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539169 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.411s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6121s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:01.654071368 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1343] 1 False 12.87
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1343'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1343', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3539240 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_854] 1 False 18.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_854'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_854', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539310 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6799s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:06.230243712 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1839] 1 False 15.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1839'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1839', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539334 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.44s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.46s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:03.839183662 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1869] 1 False 18.05
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1869'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1869', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539368 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10338s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:06.619381519 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1181] 1 False 17.21
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1181'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1181', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539697 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3007s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:10.465206857 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1606] 1 False 11.37
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1606'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1606', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3539794 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8017s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1624] 1 False 9.59
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1624'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1624', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3539844 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5875s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:03.200956171 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1075] 1 False 12.95
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1075'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1075', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3539986 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.11807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.11883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.12231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.12295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.12374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.12438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.12521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.12610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.12663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.13327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:08.537258314 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1712] 1 False 15.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1712'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1712', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3540345 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:12.139964539 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1112] 1 False 15.86
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1112'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1112', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3540999 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:15.002653781 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_933] 1 False 9.90
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_933'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_933', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3541404 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.229s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:10.154426967 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1042] 1 False 13.50
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1042'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1042', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-2' pid=3541729 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6128s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:15.447069347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-2: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1617] 1 False 14.56
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1617'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1617', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-2' pid=3541733 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1419] 1 False 12.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1419'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1419', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3542000 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7708s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.63584s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.63597s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.63602s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.63605s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.63609s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.63632s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.63645s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1907] 1 False 15.40
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1907'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1907', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3542376 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:22.045278124 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1082] 1 False 16.92
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1082'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1082', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3542727 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9061s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:25.185656076 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1327] 1 False 15.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1327'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1327', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3543106 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.811394s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.811422s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.811425s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.811427s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.811431s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.811443s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.811448s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.880855s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.880925s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.880944s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1333] 1 False 15.90
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1333'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1333', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-3' pid=3543223 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.744525s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.744559s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.744562s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.744565s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.744569s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.744579s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.744586s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.791991s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.792046s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.792066s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1570] 1 False 9.79
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1570'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1570', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-3' pid=3543229 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_863] 1 False 17.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_863'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_863', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3543451 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:29.394600769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_871] 1 False 10.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_871'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_871', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3543651 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6170s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:24.152947894 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1411] 1 False 20.90
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1411'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1411', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-4' pid=3544159 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.59s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.61s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.100354s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.100381s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.100385s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.100388s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.100393s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.100418s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.100430s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1642] 1 False 11.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1642'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1642', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3544391 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:26.821662133 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_783] 1 False 19.04
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_783'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_783', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3544425 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4236s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:34.700843407 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1117] 1 False 12.59
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1117'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1117', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3544519 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7042s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:28.319289347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1751] 1 False 9.38
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1751'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1751', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3544547 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8259s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8281s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1750] 1 False 17.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-4' pid=3544553 parent=3536629 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.37884s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.37893s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.37897s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.37899s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.37903s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.37916s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.37924s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1913] 1 False 12.49
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1913'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1913', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-3' pid=3544662 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:29.361804596 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-3: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1649] 1 False 15.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1649'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1649', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3544693 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:32.490779934 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1303] 1 False 18.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1303'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1303', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3545029 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4853s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:37.964365764 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1367] 1 False 12.19
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1367'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1367', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-4' pid=3545172 parent=3536271 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.33633s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.33639s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.33641s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.33643s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.33647s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.33658s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.33664s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.81429s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.81516s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.81528s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1645] 1 False 16.98
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1645'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1645', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3545420 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:37.646442775 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1666] 1 False 18.90
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1666'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1666', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3545476 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:39.978387939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1608] 1 False 10.60
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1608'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1608', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3545908 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1254] 1 False 11.49
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1254'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1254', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3546211 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:36.725765824 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1938] 1 False 9.64
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1938'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1938', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3546508 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.194s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2449s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:35.882730097 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_912] 1 False 16.96
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_912'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_912', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3546564 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:43.726317021 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_944] 1 False 15.50
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_944'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_944', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3546634 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5240s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:42.677086135 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1308] 1 False 15.27
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1308'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1308', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-4' pid=3546954 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5294s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:44.211798029 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1151] 1 False 9.51
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1151'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1151', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3546955 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:38.934584590 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1072] 1 False 20.05
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1072'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1072', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3547390 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:52.384974618 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1565] 1 False 16.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1565'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1565', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-6' pid=3547830 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7958s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1274] 1 False 23.57
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1274'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1274', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3547858 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.574s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9319s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:58.220536595 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1733] 1 False 16.46
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-5' pid=3548173 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.36904s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.36909s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.36911s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.36913s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.36915s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.36923s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.36929s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1337] 1 False 16.57
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1337'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1337', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-5' pid=3548663 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:53.746641358 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_826] 1 False 12.22
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_826'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_826', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3548728 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:50.157082949 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1226] 1 False 13.35
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1226'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1226', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3548980 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7438s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:52.432870591 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_958] 1 False 16.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_958'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_958', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3549273 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6524s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:56.373692593 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_708] 1 False 10.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-4' pid=3549397 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:50.917699137 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-4: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1516] 1 False 9.96
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1516'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1516', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-5' pid=3549431 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4302s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1111] 1 False 15.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1111'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1111', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3549664 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:57.918579879 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1080] 1 False 20.07
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1080'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1080', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3549969 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:06.458242940 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1859] 1 False 12.96
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1859'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1859', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3550197 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:00.603357937 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1016] 1 False 19.19
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1016'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1016', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3550482 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:08.124231721 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1687] 1 False 8.69
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1687'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1687', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3550583 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7240s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:56:58.229917508 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1476] 1 False 16.60
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1476'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1476', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-5' pid=3551007 parent=3536280 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.68155s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68179s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.68182s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.68186s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.68193s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.68215s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.68228s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1737] 1 False 12.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-6' pid=3551126 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11235s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1263] 1 False 12.28
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1263'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1263', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3551176 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:03.554340351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1060] 1 False 13.65
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1060'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1060', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-5' pid=3551629 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:06.456585224 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-5: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_651] 1 False 10.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_651'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_651', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3552099 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4296s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:06.326024799 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_641] 1 False 12.22
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_641'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_641', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3552200 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3579s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3596s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:08.711918525 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_891] 1 False 14.96
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_891'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_891', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3553097 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:15.612904795 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1088] 1 False 17.68
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1088'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1088', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3553452 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:21.057589120 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1665] 1 False 11.38
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1665'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1665', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3553610 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:16.050304516 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_782] 1 False 21.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_782'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_782', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3554051 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:27.621404833 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1430] 1 False 20.23
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1430'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1430', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3554152 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1766] 1 False 18.54
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1766'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1766', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-7' pid=3554725 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.280s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.32455s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.32461s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.32463s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.32465s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.32468s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.32479s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.32485s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1321] 1 False 11.02
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1321'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1321', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-7' pid=3554749 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11224s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.611423s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.611465s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.611467s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.611472s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.611480s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.611514s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.611532s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.659562s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.659799s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.659814s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_704] 1 False 9.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3554946 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:20.224618655 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1654] 1 False 13.61
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1654'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1654', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3555290 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4780s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:25.730661898 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1538] 1 False 13.70
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1538'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1538', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3555321 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1849] 1 False 18.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1849'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1849', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3555544 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:31.213045902 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1704] 1 False 12.86
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1704'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1704', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3555613 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8921s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:25.980990700 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1352] 1 False 15.20
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1352'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1352', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-7' pid=3555905 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.348s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:29.208406990 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1040] 1 False 15.06
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1040'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1040', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-6' pid=3556056 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:30.142739991 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-6: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1466] 1 False 11.40
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1466'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1466', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-8' pid=3556091 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1616] 1 False 10.73
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1616'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1616', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3556183 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:26.210446358 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1242] 1 False 10.24
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1242'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1242', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3556434 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4263s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4277s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:27.626307860 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1161] 1 False 16.86
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1161'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1161', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3556533 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:34.936686181 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1033] 1 False 21.17
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1033'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1033', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3557074 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:41.380259924 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1950] 1 False 15.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1950'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1950', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3557210 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:35.899186469 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_913] 1 False 13.93
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_913'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_913', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3557332 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:35.031299765 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1425] 1 False 16.35
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1425'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1425', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-8' pid=3557465 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4055s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4070s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.49848s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.49871s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.49875s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.49879s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.49888s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.49938s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.49961s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_649] 1 False 11.04
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_649'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_649', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3557985 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:36.690978571 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1193] 1 False 12.79
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1193'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1193', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-7' pid=3558021 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3100s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:38.568327110 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-7: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1468] 1 False 16.25
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1468'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1468', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-8' pid=3558097 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.151865s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.151882s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.151888s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.151892s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.151899s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.151924s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.151937s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1230] 1 False 18.23
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1230'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1230', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3558109 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:44.252910932 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1808] 1 False 14.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1808'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1808', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3558406 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6217s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:41.070722732 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1772] 1 False 12.53
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1772'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1772', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3558462 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8774s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:39.323853165 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1172] 1 False 15.27
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1172'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1172', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3558660 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7885s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:42.936099708 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_743] 1 False 19.81
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-8' pid=3558674 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8185s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8209s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_755] 1 False 15.58
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_755'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_755', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3559092 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1288] 1 False 15.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1288'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1288', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3559481 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12258s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:49.393690296 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1098] 1 False 21.64
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1098'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1098', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3559711 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:56.642910537 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1010] 1 False 16.88
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1010'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1010', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3559735 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:52.002599009 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1084] 1 False 19.68
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1084'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1084', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3559994 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4642s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:56.366846991 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_749] 1 False 14.27
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3560549 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1287] 1 False 23.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1287'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1287', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3560630 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:02.793963992 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1851] 1 False 12.19
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1851'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1851', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-8' pid=3561001 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4711s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4724s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:53.632501293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-8: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1769] 1 False 11.88
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1769'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1769', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-9' pid=3561883 parent=3536280 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.33225s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.33233s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.33236s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.33237s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.33241s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.33258s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.33264s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_837] 1 False 17.46
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_837'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_837', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3561962 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10326s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:03.664474219 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1011] 1 False 12.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1011'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1011', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3562143 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.91s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4861s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:59.411122467 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1906] 1 False 9.29
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1906'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1906', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3562521 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:57:58.780630503 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_729] 1 False 14.59
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3562753 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9206s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1604] 1 False 14.41
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1604'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1604', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3563047 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:05.602288293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_657] 1 False 13.18
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_657'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_657', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3563424 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.219s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:06.760154063 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1951] 1 False 22.25
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1951'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1951', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-9' pid=3563448 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.252s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:15.942819626 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-9: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1741] 1 False 10.93
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-10' pid=3563477 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7567s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_811] 1 False 17.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_811'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_811', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3564150 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:14.918902377 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_935] 1 False 19.28
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_935'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_935', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3564626 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:18.766687411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1729] 1 False 9.20
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1729'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1729', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-10' pid=3565054 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3942s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_747] 1 False 9.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3565174 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1539] 1 False 13.67
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1539'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1539', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-9' pid=3565219 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_779] 1 False 11.50
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_779'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_779', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3565391 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3906s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:15.225558892 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_741] 1 False 9.19
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_741'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_741', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3565644 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1374] 1 False 8.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1374'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1374', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3565703 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4904s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.36434s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.36449s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.36452s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.36455s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.36461s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.36487s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.36500s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.83763s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.83905s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.83918s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1095] 1 False 14.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1095'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1095', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3565855 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3081s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:19.615950857 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1731] 1 False 19.10
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-11' pid=3566184 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3481s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.28177s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.28185s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.28187s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.28189s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.28193s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.28205s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.28213s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1456] 1 False 15.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1456'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1456', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-10' pid=3566400 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1711] 1 False 21.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3566433 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:29.576460741 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1796] 1 False 17.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1796'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1796', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3566434 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3235s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:25.413738736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1705] 1 False 14.65
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3566746 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.564s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:25.359978931 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_931] 1 False 16.92
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_931'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_931', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3566800 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3856s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:28.150427812 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1847] 1 False 18.05
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1847'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1847', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3566925 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5103s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:30.184179354 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1140] 1 False 15.88
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1140'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1140', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3566928 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:28.032537057 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_950] 1 False 14.69
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_950'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_950', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3567164 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:27.999708741 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1622] 1 False 11.63
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1622'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1622', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3567302 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1568] 1 False 17.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1568'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1568', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-12' pid=3567394 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1897] 1 False 16.90
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1897'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1897', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3567653 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7513s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:31.816808411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_909] 1 False 16.69
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_909'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_909', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-10' pid=3567893 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:32.639117701 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-10: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1440] 1 False 18.11
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1440'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1440', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-10' pid=3567927 parent=3536424 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.95152s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.95167s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.95170s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.95174s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.95180s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.95201s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.95212s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1355] 1 False 13.37
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1355'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1355', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3568319 parent=3536274 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.66816s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.66834s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.66837s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.66839s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.66844s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.66867s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.66878s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.114984s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.115034s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.115045s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1085] 1 False 9.60
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1085'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1085', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3568442 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3955s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:28.413565255 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1908] 1 False 19.20
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1908'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1908', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3568663 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:39.530552149 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1676] 1 False 9.85
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1676'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1676', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3569348 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5287s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:35.244536092 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1220] 1 False 12.44
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1220'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1220', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3569498 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4008s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:38.534734148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1126] 1 False 13.63
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1126'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1126', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3569994 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:41.653735648 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1674] 1 False 15.75
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1674'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1674', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3570014 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:43.765726522 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1694] 1 False 17.44
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1694'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1694', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3570072 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:45.614919365 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1630] 1 False 20.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1630'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1630', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3570332 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:49.023931822 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_953] 1 False 14.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_953'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_953', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3570528 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:44.906699515 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_630] 1 False 13.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_630'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_630', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3570857 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.447s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:45.842314856 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1883] 1 False 17.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1883'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1883', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3570928 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2660s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:49.788489328 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1357] 1 False 14.40
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1357'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1357', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-11' pid=3570987 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9310s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:46.586794550 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_855] 1 False 9.15
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_855'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_855', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-11' pid=3571365 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:43.827946848 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-11: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1841] 1 False 22.21
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1841'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1841', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3571437 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12164s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:57.369652309 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1493] 1 False 16.96
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1493'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1493', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3571461 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10655s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1444] 1 False 12.58
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1444'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1444', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3571835 parent=3536460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2242s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.71141s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.71147s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.71149s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.71151s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.71154s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.71165s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.71170s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1132] 1 False 12.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1132'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1132', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3572019 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.224s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:50.940725686 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1505] 1 False 16.65
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1505'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1505', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3572059 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.577s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1744] 1 False 8.37
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1744'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1744', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3572355 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.27340s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.27347s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.27349s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.27351s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.27355s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.27365s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.27369s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1790] 1 False 21.94
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1790'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1790', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3572447 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:03.646764383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1232] 1 False 13.64
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1232'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1232', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3572756 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:56.942702710 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1667] 1 False 14.02
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1667'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1667', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3572951 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2821s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:57.805036553 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1093] 1 False 16.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1093'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1093', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3572952 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4638s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:58:59.916804365 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1662] 1 False 20.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1662'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1662', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3573133 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:05.440862223 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1567] 1 False 16.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1567'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1567', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3573455 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1764] 1 False 16.42
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1764'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1764', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-14' pid=3573616 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.52435s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.52448s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.52451s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.52454s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.52458s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.52483s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.52493s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1673] 1 False 19.66
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1673'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1673', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3573645 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:06.766498495 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1322] 1 False 10.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1322'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1322', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-12' pid=3573669 parent=3536730 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.923544s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.923561s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.923564s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.923566s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.923571s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.923586s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.923597s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.970544s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.970651s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.970665s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1770] 1 False 9.61
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1770'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1770', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-14' pid=3574169 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.42782s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.42800s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.42804s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.42807s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.42815s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.42839s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.42852s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1548] 1 False 14.02
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1548'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1548', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-14' pid=3574171 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9411s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_683] 1 False 20.45
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_683'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_683', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3574434 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:10.271363801 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1592] 1 False 16.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1592'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1592', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-15' pid=3574465 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:05.820850867 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1014] 1 False 23.45
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1014'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1014', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-12' pid=3574812 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8523s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:14.776475442 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-12: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1021] 1 False 22.46
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1021'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1021', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3574896 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9553s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9577s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:14.804477241 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_945] 1 False 22.23
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_945'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_945', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3574923 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:14.881169918 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_829] 1 False 10.47
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_829'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_829', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3575073 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:05.916483399 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_941] 1 False 14.61
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_941'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_941', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-13' pid=3575773 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4621s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:12.323682272 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-13: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1860] 1 False 11.90
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1860'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1860', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3575799 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9066s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:09.894448790 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_804] 1 False 20.76
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_804'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_804', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3575956 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8920s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:19.982947736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1498] 1 False 14.02
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1498'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1498', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3576017 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1118] 1 False 11.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1118'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1118', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3576153 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.599s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7519s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:14.178750871 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1644] 1 False 19.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1644'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1644', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3576523 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5089s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:22.805641819 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1591] 1 False 18.49
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1591'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1591', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-14' pid=3576662 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1099] 1 False 20.26
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1099'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1099', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3576809 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.583s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:24.932518513 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1752] 1 False 19.51
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1752'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1752', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-13' pid=3577067 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.74801s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.74811s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.74814s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.74817s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.74825s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.74849s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.74866s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_724] 1 False 8.77
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-15' pid=3577222 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_900] 1 False 15.90
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_900'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_900', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3577425 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:22.745687490 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1778] 1 False 10.97
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1778'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1778', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3577954 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:20.381206625 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1647] 1 False 22.15
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1647'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1647', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3578057 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8398s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:31.869182521 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1677] 1 False 13.83
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1677'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1677', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3578107 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3696s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:23.711817137 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1924] 1 False 20.24
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1924'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1924', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3578173 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:30.610749014 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_781] 1 False 9.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_781'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_781', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3578335 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:21.929344965 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_748] 1 False 15.83
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-13' pid=3579056 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1728] 1 False 11.61
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3579059 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.35053s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.35062s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.35063s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.35065s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.35070s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.35083s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.35089s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1455] 1 False 21.69
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1455'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1455', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-15' pid=3579076 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:36.266844602 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1536] 1 False 16.12
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1536'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1536', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3579244 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.391s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_750] 1 False 13.03
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_750'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_750', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3579293 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1285] 1 False 17.32
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1285'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1285', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3579436 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5786s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:35.633111342 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1454] 1 False 15.76
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1454'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1454', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3579804 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1324] 1 False 11.07
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1324'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1324', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3580106 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.779220s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.779257s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.779260s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.779263s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.779271s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.779298s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.779314s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.827742s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.827860s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.827875s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1946] 1 False 11.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1946'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1946', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3580584 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:33.918474036 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1200] 1 False 18.02
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1200'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1200', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3580585 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4052s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4070s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:40.764731932 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1823] 1 False 13.86
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1823'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1823', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3580609 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2746s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2754s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:36.657991243 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_692] 1 False 13.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_692'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_692', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3580659 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:36.229768589 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1854] 1 False 20.73
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1854'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1854', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3580937 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:44.723495286 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1306] 1 False 14.65
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1306'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1306', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-15' pid=3581125 parent=3536289 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.516621s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.516649s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.516652s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.516654s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.516659s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.516669s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.516672s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.563161s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.563285s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.563300s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1387] 1 False 9.90
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1387'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1387', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-17' pid=3581497 parent=3536562 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.31290s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.31297s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.31299s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.31302s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.31305s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.31317s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.31322s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.79044s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.79146s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.79158s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1116] 1 False 13.34
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1116'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1116', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3581521 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:42.765531835 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1469] 1 False 10.57
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1469'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1469', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-16' pid=3581880 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.58864s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.58872s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.58876s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.58878s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.58881s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.58896s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.58902s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_824] 1 False 22.66
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_824'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_824', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-14' pid=3581919 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5032s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5043s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:53.360855371 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-14: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_845] 1 False 13.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_845'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_845', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3581998 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6555s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:44.215453382 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1223] 1 False 13.87
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1223'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1223', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3582111 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4047s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:45.490095690 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1672] 1 False 16.57
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1672'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1672', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3582137 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6388s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:48.385786020 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1901] 1 False 22.07
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1901'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1901', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3582387 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8289s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:56.040285026 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1074] 1 False 21.55
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1074'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1074', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3582849 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:57.346107492 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_834] 1 False 18.61
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_834'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_834', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3583006 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:54.843398828 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_806] 1 False 18.00
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_806'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_806', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3583056 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:54.632401430 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1018] 1 False 10.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1018'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1018', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3583088 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7926s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:47.010224902 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1874] 1 False 10.99
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1874'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1874', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3583840 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3987s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:51.825051062 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1519] 1 False 8.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1519'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1519', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-16' pid=3584128 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3848s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3867s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1740] 1 False 9.17
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3584129 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4609s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1487] 1 False 10.04
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1487'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1487', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3584179 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_639] 1 False 19.85
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_639'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_639', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3584375 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6529s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6554s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:02.731453149 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1252] 1 False 12.76
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1252'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1252', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3584447 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3534s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3546s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:55.744914442 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1213] 1 False 19.58
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1213'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1213', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3584625 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9133s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:03.808086453 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1331] 1 False 16.62
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1331'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1331', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3584751 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4717s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:01.785003524 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1234] 1 False 15.99
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1234'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1234', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3585038 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:03.010024733 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_859] 1 False 10.23
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_859'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_859', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3585083 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.649s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 03:59:57.641980621 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1391] 1 False 11.78
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1391'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1391', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3585385 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10507s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.67735s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.67747s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.67750s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.67754s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.67758s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.67783s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.67795s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.114631s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.114733s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.114748s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1188] 1 False 19.75
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1188'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1188', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3585390 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7504s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:10.353644625 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1715] 1 False 10.15
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3585893 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:02.002674908 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1779] 1 False 21.00
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1779'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1779', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3585894 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3610s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:12.897101312 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1283] 1 False 21.67
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1283'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1283', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3586412 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:14.809106875 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1049] 1 False 15.74
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1049'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1049', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-15' pid=3586496 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3975s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3989s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:09.132395490 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-15: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1209] 1 False 14.62
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1209'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1209', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3586520 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:08.103315676 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1784] 1 False 21.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1784'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1784', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3586544 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:15.380976456 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1724] 1 False 16.92
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1724'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1724', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-17' pid=3586833 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4048s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1502] 1 False 23.01
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1502'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1502', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-17' pid=3587033 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9667s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_778] 1 False 21.55
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_778'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_778', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3587345 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:19.199999703 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1765] 1 False 11.35
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1765'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1765', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3587385 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9250s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1845] 1 False 9.44
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1845'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1845', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3587568 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5618s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5634s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:09.593016781 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1009] 1 False 12.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1009'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1009', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3587923 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7701s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:14.211785302 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1050] 1 False 11.67
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1050'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1050', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3587988 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6654s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:13.955898232 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1246] 1 False 17.46
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1246'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1246', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3588202 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8760s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:20.205209594 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1437] 1 False 10.12
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1437'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1437', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3588788 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5321s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1599] 1 False 13.66
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1599'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1599', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3588818 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:19.675321594 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1203] 1 False 9.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1203'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1203', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3589133 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:17.193540158 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1722] 1 False 16.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3589162 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:24.281845906 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1295] 1 False 16.55
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1295'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1295', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-16' pid=3589470 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:25.702005854 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-16: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1540] 1 False 18.52
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1540'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1540', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-19' pid=3589547 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1574] 1 False 14.91
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1574'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1574', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-18' pid=3589591 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.414s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5175s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_903] 1 False 13.80
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_903'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_903', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3590406 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:27.683566685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1954] 1 False 21.18
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1954'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1954', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3590451 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:35.114376293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_762] 1 False 15.94
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_762'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_762', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3590513 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.632s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_848] 1 False 16.72
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_848'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_848', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-18' pid=3590636 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:31.573631886 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-18: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1834] 1 False 13.96
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1834'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1834', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3590685 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8917s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:29.384351805 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1836] 1 False 10.43
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1836'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1836', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3590898 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4000s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:26.878393271 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1394] 1 False 13.33
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1394'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1394', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3591316 parent=3536460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.72914s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.72922s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.72924s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.72926s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.72932s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.72948s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.72959s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.121829s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.121943s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.121960s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1788] 1 False 12.90
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1788'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1788', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3591390 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:32.190559874 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1416] 1 False 11.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1416'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1416', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-18' pid=3591570 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.89495s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.89508s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.89512s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.89516s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.89521s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.89544s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.89563s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1415] 1 False 12.69
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1415'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1415', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-21' pid=3591857 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5159s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5178s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.69717s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.69747s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.69753s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.69757s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.69766s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.69797s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.69813s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
tcache_thread_shutdown(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_822] 1 False 15.16
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_822'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_822', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3592207 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:39.544589149 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1103] 1 False 20.24
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1103'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1103', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-19' pid=3592265 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:44.825006587 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-19: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_906] 1 False 23.33
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_906'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_906', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-17' pid=3592543 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10050s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:49.038327813 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-17: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1625] 1 False 13.41
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1625'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1625', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3593048 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1039] 1 False 9.67
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1039'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1039', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3593415 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6078s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:39.969686935 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1426] 1 False 19.45
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1426'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1426', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-19' pid=3593821 parent=3536289 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9812s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.101437s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.101448s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.101451s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.101455s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.101460s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.101486s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.101501s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1732] 1 False 15.16
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-21' pid=3593942 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.75416s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.75429s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.75432s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.75436s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.75441s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.75469s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.75485s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1943] 1 False 9.67
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1943'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1943', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3593980 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:41.953442689 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1601] 1 False 15.43
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1601'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1601', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-19' pid=3593981 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5485s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:47.306157366 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1351] 1 False 15.72
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1351'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1351', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-21' pid=3594244 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.35811s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.35820s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.35824s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.35826s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.35830s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.35842s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.35848s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.83576s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.83709s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.83723s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1503] 1 False 9.78
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1503'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1503', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3594320 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.410s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1100] 1 False 14.32
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1100'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1100', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3594812 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:50.582136413 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1005] 1 False 18.44
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1005'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1005', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3594866 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:55.228256426 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1463] 1 False 11.17
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1463'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1463', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-23' pid=3595132 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.93899s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.93909s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.93912s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.93916s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.93920s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.93935s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.93944s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_684] 1 False 19.60
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_684'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_684', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3595506 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10480s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:01.079895127 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1755] 1 False 11.09
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1755'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1755', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-21' pid=3595601 parent=3536730 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.75330s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.75340s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.75342s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.75347s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.75355s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.75384s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.75400s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_897] 1 False 15.29
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_897'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_897', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3595706 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6366s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:57.235237683 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1339] 1 False 16.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1339'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1339', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3595781 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8509s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:58.255039340 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1760] 1 False 17.99
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1760'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1760', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3595846 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1142] 1 False 9.01
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1142'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1142', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3596140 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:53.895686901 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1915] 1 False 11.27
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1915'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1915', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3596546 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4088s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:00:59.007440931 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1719] 1 False 17.05
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-20' pid=3596611 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8255s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:04.853074598 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-20: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1480] 1 False 15.63
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1480'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1480', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-22' pid=3596879 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9593s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.132454s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.132467s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.132470s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.132474s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.132479s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.132504s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.132521s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_947] 1 False 23.85
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_947'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_947', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3597246 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:14.509779261 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_742] 1 False 19.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_742'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_742', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3597435 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9992s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_666] 1 False 14.09
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_666'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_666', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3597604 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:05.793889695 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1182] 1 False 12.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1182'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1182', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3597921 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:05.855914048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1457] 1 False 9.97
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1457'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1457', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3597964 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5252s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1822] 1 False 15.18
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1822'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1822', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3598252 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:09.944511736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1884] 1 False 16.98
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1884'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1884', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3598349 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:12.284343253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_882] 1 False 9.41
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_882'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_882', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3598853 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4288s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:08.223597468 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_954] 1 False 15.07
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_954'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_954', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3598887 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8313s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:14.185421110 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_868] 1 False 21.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_868'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_868', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3599225 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:22.440446574 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1758] 1 False 11.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1758'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1758', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-23' pid=3599644 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.55174s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.55185s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.55188s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.55190s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.55195s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.55220s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.55234s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_926] 1 False 17.70
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_926'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_926', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3599941 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:22.502318191 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1580] 1 False 17.67
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1580'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1580', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3600157 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_895] 1 False 9.83
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_895'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_895', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3600158 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:15.795015668 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1276] 1 False 17.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1276'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1276', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3600452 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:24.777046791 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1404] 1 False 20.79
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1404'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1404', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3600544 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.574s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9883s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1094] 1 False 11.97
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1094'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1094', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-22' pid=3601066 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:22.078629101 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-22: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_817] 1 False 12.61
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_817'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_817', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-21' pid=3601168 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4346s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:23.210659859 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-21: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1555] 1 False 9.26
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1555'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1555', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3601196 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1561] 1 False 9.53
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1561'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1561', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3601500 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_930] 1 False 20.74
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_930'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_930', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3601563 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4487s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:33.071775038 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1530] 1 False 10.47
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1530'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1530', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3601683 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7932s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_726] 1 False 16.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3602278 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4339s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1842] 1 False 16.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1842'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1842', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3602424 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9445s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9476s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:32.442031282 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_949] 1 False 18.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_949'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_949', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3602504 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2996s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:38.851984535 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1806] 1 False 14.24
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1806'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1806', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3603172 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:36.315205528 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1955] 1 False 11.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1955'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1955', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3603245 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4604s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:33.525845290 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1542] 1 False 12.68
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1542'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1542', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-24' pid=3603398 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1353] 1 False 15.32
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1353'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1353', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-21' pid=3603504 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.239s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:37.715380009 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1378] 1 False 14.75
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1378'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1378', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-22' pid=3603638 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:37.705598365 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_918] 1 False 17.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_918'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_918', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3603747 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:40.737524393 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1312] 1 False 13.86
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1312'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1312', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-20' pid=3603971 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:38.175669373 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_752] 1 False 14.80
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_752'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_752', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3604133 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1610] 1 False 13.36
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1610'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1610', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3604469 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:39.682789268 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1931] 1 False 10.02
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1931'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1931', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3604523 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:37.303943645 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1657] 1 False 19.84
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1657'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1657', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3604707 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:48.435298896 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1136] 1 False 22.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1136'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1136', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3604819 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:51.683423933 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1238] 1 False 19.19
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1238'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1238', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3605168 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2547s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:51.717372008 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1388] 1 False 19.20
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1388'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1388', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-24' pid=3605349 parent=3536424 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8170s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.59641s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.59653s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.59656s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.59659s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.59663s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.59681s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.59692s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.115944s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.116016s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.116027s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1008] 1 False 15.84
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1008'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1008', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3605648 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:51.176310649 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_885] 1 False 16.77
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_885'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_885', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3605896 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:53.143736061 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1020] 1 False 9.40
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1020'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1020', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3606165 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3841s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:46.563199072 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1768] 1 False 10.51
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1768'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1768', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3606534 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3687s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1664] 1 False 13.87
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1664'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1664', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3606656 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:52.192948721 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1271] 1 False 10.08
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1271'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1271', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3607002 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3689s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:50.112988076 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1201] 1 False 16.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1201'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1201', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3607135 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:01:57.122043199 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1362] 1 False 15.80
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1362'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1362', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3607800 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:02.161850514 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1868] 1 False 13.14
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1868'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1868', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3608190 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9199s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:01.694295715 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1855] 1 False 17.45
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1855'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1855', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-23' pid=3608739 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2490s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:07.945123697 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-23: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_828] 1 False 19.13
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_828'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_828', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3608998 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8752s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:10.303970250 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1336] 1 False 16.13
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1336'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1336', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-26' pid=3609132 parent=3536730 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7913s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.566842s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.566864s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.566866s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.566868s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.566872s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.566887s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.566895s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.614455s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.614733s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.614745s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_740] 1 False 12.84
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_740'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_740', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3609131 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1004] 1 False 9.87
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1004'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1004', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3609218 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:01.929031255 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1097] 1 False 18.92
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1097'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1097', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3609339 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:11.239830360 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1179] 1 False 10.36
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1179'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1179', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3609587 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5556s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:03.568766180 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_774] 1 False 18.80
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_774'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_774', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3609650 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:12.529895395 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1810] 1 False 9.01
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1810'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1810', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3610004 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:06.194567253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_951] 1 False 11.43
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_951'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_951', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3610028 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3675s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:08.688570797 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1736] 1 False 12.93
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3610981 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10191s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1038] 1 False 17.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1038'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1038', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3611240 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3214s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:20.439007859 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_737] 1 False 11.88
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_737'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_737', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3611310 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1137] 1 False 11.05
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1137'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1137', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3611557 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:16.178662079 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1365] 1 False 10.00
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1365'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1365', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-28' pid=3611806 parent=3536268 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.38770s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.38783s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.38787s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.38790s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.38797s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.38817s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.38827s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.95746s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.95854s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.95866s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_738] 1 False 9.41
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3612059 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_899] 1 False 14.33
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_899'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_899', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3612344 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:22.221011259 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1659] 1 False 16.85
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1659'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1659', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-24' pid=3612358 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:24.791606980 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-24: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1197] 1 False 20.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1197'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1197', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3612560 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:29.199841361 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1390] 1 False 12.30
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1390'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1390', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-28' pid=3612561 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.63417s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.63430s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.63435s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.63438s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.63446s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.63470s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.63481s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.110527s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.110653s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.110667s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1133] 1 False 20.51
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1133'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1133', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3612786 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:30.853800558 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1684] 1 False 17.41
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1684'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1684', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3612939 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4711s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:28.639784878 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1186] 1 False 23.71
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1186'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1186', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3613074 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10314s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:35.596337147 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1145] 1 False 23.50
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1145'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1145', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3613137 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8351s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:36.084725789 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1478] 1 False 10.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1478'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1478', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-28' pid=3613443 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.107700s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.107718s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.107721s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.107724s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.107728s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.107753s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.107764s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1120] 1 False 13.84
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1120'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1120', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3613733 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:29.384174368 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1569] 1 False 14.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1569'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1569', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3613778 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1227] 1 False 16.40
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1227'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1227', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3613857 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:32.396175577 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1059] 1 False 11.83
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1059'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1059', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3613902 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.649s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:28.060290415 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_907] 1 False 11.56
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_907'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_907', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3614107 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.435s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8072s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:28.854383472 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1165] 1 False 15.01
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1165'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1165', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3614393 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4194s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:33.658715605 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1372] 1 False 8.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1372'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1372', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-23' pid=3614527 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:27.972627680 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_720] 1 False 12.61
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3614528 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.261s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4480s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:32.029581245 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1087] 1 False 14.69
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1087'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1087', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3614768 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:35.278220384 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1302] 1 False 14.87
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1302'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1302', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3615418 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6528s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:39.705373064 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_670] 1 False 15.48
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_670'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_670', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-25' pid=3615423 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:40.302224148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-25: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_764] 1 False 13.21
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_764'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_764', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-26' pid=3615518 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1643] 1 False 19.46
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1643'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1643', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3615519 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4244s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:44.722834597 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1763] 1 False 17.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1763'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1763', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3615974 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8346s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1838] 1 False 15.93
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1838'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1838', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3616363 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:45.150458264 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_928] 1 False 18.55
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_928'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_928', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3616388 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7946s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:48.019360212 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1041] 1 False 13.39
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1041'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1041', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3616422 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3203s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:43.301105441 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_673] 1 False 12.06
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_673'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_673', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3616505 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:43.008105063 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_905] 1 False 13.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_905'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_905', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3616808 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:45.797788475 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1767] 1 False 9.10
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1767'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1767', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-29' pid=3617004 parent=3536730 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4798s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.34671s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.34686s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.34688s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.34689s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.34693s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.34707s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.34714s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_869] 1 False 14.16
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_869'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_869', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3617241 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:47.889464756 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1821] 1 False 16.89
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1821'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1821', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3617265 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:50.708825701 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1294] 1 False 23.38
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1294'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1294', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3617674 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10307s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:58.628391597 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1497] 1 False 19.08
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1497'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1497', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3617747 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6354s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1571] 1 False 11.03
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1571'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1571', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3617801 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3543s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1393] 1 False 10.39
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1393'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1393', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3617885 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:46.129294185 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1563] 1 False 17.23
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1563'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1563', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3617968 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_780] 1 False 14.63
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_780'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_780', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3618353 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:54.320170803 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1396] 1 False 22.39
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1396'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1396', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-30' pid=3618418 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3678s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.28157s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.28167s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.28168s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.28169s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.28173s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.28189s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.28194s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.75457s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.75558s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.75570s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1015] 1 False 12.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1015'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1015', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-26' pid=3618419 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:52.641166383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-26: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1377] 1 False 20.57
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1377'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1377', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3618690 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.583s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10839s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:02.086703497 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1250] 1 False 19.46
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1250'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1250', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3619038 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:02.302629844 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1504] 1 False 22.41
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1504'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1504', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-27' pid=3619043 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.625s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8962s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1130] 1 False 12.59
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1130'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1130', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3619109 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.218s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3676s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:02:55.663621109 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1655] 1 False 18.21
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1655'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1655', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3619210 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:01.542929578 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1462] 1 False 10.70
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1462'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1462', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3619525 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1605] 1 False 9.15
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1605'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1605', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3619721 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1886] 1 False 13.44
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1886'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1886', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3619802 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:00.026859632 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1639] 1 False 18.24
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1639'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1639', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3620199 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:06.253082378 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1047] 1 False 19.65
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1047'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1047', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3620225 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3707s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:07.913795517 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_711] 1 False 18.56
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_711'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_711', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3620463 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:09.287060902 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1036] 1 False 12.73
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1036'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1036', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3620650 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:04.428621252 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1077] 1 False 10.58
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1077'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1077', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-27' pid=3620762 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:03.274172186 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-27: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1939] 1 False 15.77
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1939'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1939', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3621098 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8571s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:10.171901680 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_719] 1 False 16.88
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_719'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_719', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3621190 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:11.383388098 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1816] 1 False 13.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1816'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1816', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3621243 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6617s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:08.245189935 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1031] 1 False 10.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1031'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1031', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3621448 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.12791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.12846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.12920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.12983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.13626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.13693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.13738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.13825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.13896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.13954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:05.180740757 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_835] 1 False 17.79
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_835'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_835', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3621518 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2788s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:13.329559529 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_769] 1 False 14.07
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_769'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_769', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3621560 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8753s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1947] 1 False 15.25
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1947'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1947', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3622050 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:15.067536250 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_879] 1 False 9.88
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_879'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_879', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3622353 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:11.421132043 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1256] 1 False 15.49
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1256'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1256', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-28' pid=3622755 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4119s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:18.794713519 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-28: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1409] 1 False 9.46
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1409'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1409', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-31' pid=3623072 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3030s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.86205s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.86217s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.86222s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.86225s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.86231s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.86259s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.86269s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1524] 1 False 18.51
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1524'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1524', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3623073 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1180] 1 False 17.97
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1180'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1180', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3623234 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:24.313688518 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1251] 1 False 13.63
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1251'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1251', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3623433 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:20.835790091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_904] 1 False 11.83
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_904'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_904', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3623622 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:19.820212689 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1418] 1 False 15.92
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1418'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1418', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3623774 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1957] 1 False 22.95
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1957'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1957', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-29' pid=3624070 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:32.265354087 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-29: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1202] 1 False 13.96
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1202'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1202', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3624117 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7086s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:23.498775337 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_846] 1 False 10.33
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_846'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_846', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3624210 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4898s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:20.135093712 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1602] 1 False 12.27
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1602'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1602', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-33' pid=3624549 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1279] 1 False 17.83
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1279'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1279', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3624848 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:30.073473487 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_851] 1 False 22.53
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_851'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_851', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3625147 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4935s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4955s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:35.917563224 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1293] 1 False 17.02
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1293'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1293', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3625238 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:30.861998356 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1513] 1 False 11.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1513'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1513', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3625522 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4073s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1149] 1 False 11.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1149'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1149', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3626088 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:31.326116249 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_832] 1 False 10.83
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_832'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_832', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3626920 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:34.605764621 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1607] 1 False 9.57
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1607'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1607', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-29' pid=3626953 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3912s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_943] 1 False 22.59
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_943'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_943', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3627072 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:46.925132393 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1680] 1 False 11.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1680'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1680', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3627246 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:36.443974526 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1410] 1 False 17.12
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1410'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1410', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-30' pid=3627247 parent=3536831 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6677s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.87237s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.87249s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.87253s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.87257s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.87261s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.87285s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.87299s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1658] 1 False 10.16
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1658'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1658', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3627433 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:36.057267409 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1576] 1 False 17.11
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1576'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1576', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-30' pid=3627521 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_694] 1 False 11.04
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_694'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_694', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3628053 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.224s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:41.952508815 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_699] 1 False 15.51
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_699'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_699', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3628277 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4603s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:47.002141248 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1593] 1 False 20.98
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1593'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1593', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3628444 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1338] 1 False 16.96
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1338'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1338', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-33' pid=3628468 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.421632s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.421662s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.421664s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.421667s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.421670s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.421681s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.421689s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.469166s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.469308s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.469320s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_690] 1 False 10.52
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_690'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_690', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3628492 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7002s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:42.862020296 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1300] 1 False 21.00
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1300'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1300', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3629441 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3820s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:56.939430090 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1217] 1 False 11.95
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1217'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1217', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3629596 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.604s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:49.485709525 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1257] 1 False 17.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1257'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1257', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3629845 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3826s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:57.194192719 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_686] 1 False 19.51
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_686'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_686', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3630077 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:00.033787690 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1379] 1 False 10.48
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1379'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1379', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-34' pid=3630147 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8341s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.64237s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.64248s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.64251s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.64254s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.64260s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.64287s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.64299s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.113127s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.113222s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.113237s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1368] 1 False 10.14
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1368'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1368', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-31' pid=3630619 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:51.853132250 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_867] 1 False 19.81
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_867'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_867', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3630743 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:02.723133864 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1205] 1 False 9.58
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1205'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1205', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-32' pid=3631141 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5715s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:03:54.013779442 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-32: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1460] 1 False 23.35
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1460'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1460', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-31' pid=3631219 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.9300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.9638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.11019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.11115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.12057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.12159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.12235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.155993s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.156008s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.156011s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.156013s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.156018s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.156044s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.156061s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1802] 1 False 12.60
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1802'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1802', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3631723 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7610s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:01.789190989 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1358] 1 False 15.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1358'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1358', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3631761 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3737s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:04.951579840 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1127] 1 False 14.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1127'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1127', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3632170 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7153s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7182s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:05.920700421 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1511] 1 False 11.64
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1511'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1511', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-28' pid=3632202 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1865] 1 False 17.62
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1865'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1865', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3632207 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:09.176808604 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1429] 1 False 11.14
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1429'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1429', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3632362 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.263s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2152s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_849] 1 False 18.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_849'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_849', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3632507 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.406s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:11.485604686 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1669] 1 False 14.65
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1669'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1669', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3632752 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:08.752607685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1510] 1 False 15.68
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1510'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1510', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3632881 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1858] 1 False 10.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1858'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1858', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3633315 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3627s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:07.446341028 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1244] 1 False 9.92
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1244'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1244', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3633383 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:07.097312541 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1292] 1 False 20.93
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1292'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1292', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3633505 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3708s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:19.150743239 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_823] 1 False 11.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_823'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_823', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3634030 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:11.796699583 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_702] 1 False 16.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_702'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_702', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3634054 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4043s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:16.487399066 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1522] 1 False 13.50
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1522'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1522', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3634089 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8267s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8291s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_820] 1 False 17.78
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_820'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_820', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3634257 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8867s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:18.992000646 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1514] 1 False 15.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1514'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1514', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3634543 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1405] 1 False 22.13
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1405'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1405', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-32' pid=3634620 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8122s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.78447s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.78465s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.78470s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.78474s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.78482s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.78501s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.78514s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1656] 1 False 23.50
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1656'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1656', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3634682 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3891s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:27.027265372 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_938] 1 False 15.32
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_938'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_938', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3635344 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:22.824037351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1739] 1 False 16.78
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-32' pid=3635648 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8758s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8790s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.73385s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.73397s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.73400s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.73403s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.73412s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.73440s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.73464s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_818] 1 False 14.17
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_818'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_818', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3635706 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9259s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:23.034800159 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1879] 1 False 13.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1879'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1879', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3635744 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:22.447477454 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1248] 1 False 14.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1248'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1248', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3635768 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:23.446764921 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1515] 1 False 13.63
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1515'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1515', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-36' pid=3636086 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_875] 1 False 19.87
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_875'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_875', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3636407 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3541s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:33.443131331 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1660] 1 False 12.04
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1660'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1660', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3636431 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8694s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8722s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:25.752901603 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1899] 1 False 14.95
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1899'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1899', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-30' pid=3636948 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:30.813818833 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-30: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1253] 1 False 20.13
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1253'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1253', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3636987 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:36.152551719 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1523] 1 False 13.96
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1523'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1523', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3637099 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6410s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1309] 1 False 20.57
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1309'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1309', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3637170 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6459s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:36.803368948 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1028] 1 False 21.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1028'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1028', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3637320 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3697s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:38.580906714 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1383] 1 False 15.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1383'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1383', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3637608 parent=3536274 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.220s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.40622s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.40632s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.40635s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.40637s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.40640s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.40658s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.40670s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.87792s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.87873s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.87885s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1753] 1 False 15.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1753'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1753', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3638110 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.192s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1627] 1 False 13.45
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1627'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1627', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3638326 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10984s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11013s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1918] 1 False 20.36
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1918'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1918', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3638691 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:45.258835476 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1546] 1 False 10.28
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1546'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1546', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-35' pid=3638973 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_788] 1 False 17.79
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_788'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_788', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3639074 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9165s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:44.065378654 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_687] 1 False 16.05
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_687'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_687', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3639151 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3422s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:42.791647712 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_901] 1 False 10.91
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_901'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_901', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3639282 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:38.008303960 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1678] 1 False 14.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1678'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1678', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3639419 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4978s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:42.708594173 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1483] 1 False 21.10
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1483'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1483', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3639443 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.81176s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.81188s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.81191s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.81194s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.81199s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.81223s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.81238s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1832] 1 False 17.31
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1832'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1832', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3639612 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:47.475367452 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1174] 1 False 10.86
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1174'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1174', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-31' pid=3639711 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8617s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:41.707019685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-31: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1853] 1 False 12.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1853'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1853', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3639948 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9193s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:44.437321972 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1799] 1 False 16.85
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1799'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1799', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3639972 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.11465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.11591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.11661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.11775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.11869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.11947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.11997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.12877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.12955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.13964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:49.199706591 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_735] 1 False 15.77
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-34' pid=3640192 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1547] 1 False 9.21
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1547'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1547', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3640349 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1069] 1 False 14.38
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1069'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1069', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3640702 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:50.600756372 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1618] 1 False 21.81
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1618'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1618', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-36' pid=3640863 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:58.400864872 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_713] 1 False 10.65
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3641452 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:50.877140874 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1428] 1 False 17.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1428'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1428', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-32' pid=3641808 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1682] 1 False 14.03
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1682'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1682', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3642098 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5217s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:56.831823402 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1628] 1 False 11.86
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1628'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1628', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-39' pid=3642348 parent=3536274 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753] 0.68016s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68051s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.68053s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.68055s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.68060s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.68075s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.68105s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:54.995457124 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. Process Process-39:
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_874] 1 False 13.56
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_874'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_874', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3642528 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11773s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11800s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:58.057197451 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1857] 1 False 12.51
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1857'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1857', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-34' pid=3642639 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3820s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:57.836793319 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-34: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_957] 1 False 10.03
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_957'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_957', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3642959 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9509s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:04:57.449016065 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1163] 1 False 13.87
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1163'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1163', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3642986 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:01.437719253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_647] 1 False 16.73
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_647'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_647', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3643227 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2948s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:05.956617905 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1544] 1 False 11.94
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1544'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1544', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3643401 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3212s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3225s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1191] 1 False 14.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1191'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1191', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3643639 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3304s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:04.919021453 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_665] 1 False 16.21
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_665'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_665', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3643715 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.257s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:06.784733511 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1488] 1 False 9.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1488'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1488', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-39' pid=3643879 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4058s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4075s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_703] 1 False 22.80
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3643946 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:14.712525093 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1594] 1 False 15.84
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1594'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1594', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3644183 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6349s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1703] 1 False 20.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1703'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1703', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3644184 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:13.995530934 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1587] 1 False 9.84
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1587'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1587', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3644441 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:04.994315736 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1090] 1 False 11.46
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1090'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1090', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3644475 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:07.291854411 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_721] 1 False 14.69
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3644733 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.709s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:11.551466158 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1803] 1 False 12.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1803'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1803', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3644978 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:10.853125057 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1373] 1 False 17.89
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1373'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1373', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-38' pid=3645053 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:15.493486314 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1364] 1 False 19.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1364'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1364', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-37' pid=3645245 parent=3536359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9852s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.76266s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.76278s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.76282s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.76286s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.76290s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.76316s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.76331s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.134081s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.134170s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.134185s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1932] 1 False 14.56
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1932'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1932', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-33' pid=3645320 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:13.748208956 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-33: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1882] 1 False 12.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1882'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1882', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3645378 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:11.806566559 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1706] 1 False 22.65
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3645599 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6595s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:23.609886128 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1675] 1 False 11.56
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1675'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1675', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3645862 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:13.374509830 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1406] 1 False 13.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1406'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1406', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-39' pid=3646125 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4759s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.42835s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.42844s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.42848s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.42850s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.42853s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.42864s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.42872s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1549] 1 False 13.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1549'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1549', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3646550 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9343s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9371s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1872] 1 False 18.07
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1872'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1872', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3646805 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:24.093251918 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_722] 1 False 11.71
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_722'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_722', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3646910 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.585s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1061] 1 False 11.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1061'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1061', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3647545 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4267s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:23.389867282 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1381] 1 False 8.73
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1381'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1381', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-40' pid=3647988 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7079s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.56926s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.56939s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.56941s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.56944s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.56950s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.56972s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.56985s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.104740s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.104878s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.104889s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_701] 1 False 16.86
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3648109 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9409s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:30.951658781 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1586] 1 False 18.49
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1586'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1586', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3648197 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.638s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:32.772000571 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1870] 1 False 14.06
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1870'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1870', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3648234 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:29.173080804 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1081] 1 False 21.31
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1081'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1081', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3648705 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:39.463562468 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1777] 1 False 12.84
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1777'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1777', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3648706 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:31.107632224 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1233] 1 False 13.28
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1233'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1233', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3648763 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:31.883591015 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1925] 1 False 10.18
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1925'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1925', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3649232 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:31.217819581 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_866] 1 False 10.75
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_866'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_866', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3649233 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8456s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:31.802661137 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1921] 1 False 15.43
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1921'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1921', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3649290 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:36.665693041 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1267] 1 False 16.34
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1267'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1267', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3649425 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4388s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:38.573588058 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1208] 1 False 21.70
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1208'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1208', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3649798 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:45.069137951 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1582] 1 False 11.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1582'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1582', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3649855 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1543] 1 False 12.65
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1543'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1543', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3650194 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.579s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9248s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1055] 1 False 9.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1055'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1055', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3650218 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:35.462992505 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1067] 1 False 16.30
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1067'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1067', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3650356 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:44.233750424 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1229] 1 False 10.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1229'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1229', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3650581 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:39.888012161 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_873] 1 False 14.06
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_873'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_873', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3650876 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3954s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:44.032940745 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1746] 1 False 19.77
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1746'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1746', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3650916 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8249s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1106] 1 False 20.12
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1106'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1106', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-37' pid=3651283 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10508s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:51.104702493 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-37: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_658] 1 False 16.64
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_658'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_658', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3651412 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.614s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10222s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:47.899943842 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_676] 1 False 9.38
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_676'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_676', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3652266 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:44.870010083 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1063] 1 False 17.31
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1063'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1063', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-35' pid=3652461 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:54.370779383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-35: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1212] 1 False 20.13
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1212'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1212', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3652745 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:58.729128641 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1167] 1 False 13.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1167'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1167', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3652746 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:51.856284095 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1613] 1 False 20.93
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1613'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1613', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3652897 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:00.169576284 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1228] 1 False 12.90
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1228'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1228', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3652990 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9346s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:52.869257840 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1589] 1 False 10.83
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1589'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1589', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3653189 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:51.807981783 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1171] 1 False 10.15
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1171'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1171', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3653426 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6245s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6261s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:52.464295920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1495] 1 False 13.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1495'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1495', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3653676 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.584s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_731] 1 False 11.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_731'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_731', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-40' pid=3653677 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4718s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1314] 1 False 17.30
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1314'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1314', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-44' pid=3653942 parent=3536274 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.246483s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.246515s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.246519s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.246521s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.246526s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.246540s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.246546s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.294440s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.294559s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.294571s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_771] 1 False 14.18
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_771'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_771', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3654108 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3371s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:59.105587682 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1259] 1 False 19.40
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1259'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1259', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3654132 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7955s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:04.532614809 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1114] 1 False 12.81
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1114'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1114', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3654320 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:05:59.520875100 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_888] 1 False 17.88
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_888'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_888', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3654503 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10630s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:05.874389028 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_775] 1 False 13.91
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_775'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_775', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3654972 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:03.854757839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_638] 1 False 15.53
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_638'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_638', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3655019 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:05.671586437 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_716] 1 False 16.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-40' pid=3655161 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:06.823849884 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-40: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_936] 1 False 19.31
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_936'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_936', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3655633 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:11.434399063 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1301] 1 False 15.42
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1301'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1301', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3655688 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:07.831121623 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1525] 1 False 13.98
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1525'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1525', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3655726 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1386] 1 False 11.07
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1386'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1386', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3655760 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.40s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.650s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:03.701039057 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1043] 1 False 17.87
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1043'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1043', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-36' pid=3656035 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:12.242747131 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-36: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1048] 1 False 11.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1048'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1048', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3656068 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:05.754194070 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1912] 1 False 12.39
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1912'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1912', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3656156 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:07.267839559 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1856] 1 False 15.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1856'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1856', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3656290 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.46s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.53s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7447s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7470s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:11.278563954 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1155] 1 False 14.83
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1155'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1155', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3656314 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3792s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3802s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:11.153140224 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1356] 1 False 16.75
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1356'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1356', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3656619 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3383s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:15.177779433 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1422] 1 False 9.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1422'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1422', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-40' pid=3657106 parent=3536831 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3725s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.41881s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.41890s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.41892s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.41895s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.41898s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.41910s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.41917s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_884] 1 False 10.80
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_884'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_884', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3657282 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4087s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:12.891632299 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1577] 1 False 16.61
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1577'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1577', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3657646 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1037] 1 False 14.20
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1037'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1037', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3658176 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3484s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3496s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:19.926641441 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1866] 1 False 17.49
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1866'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1866', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3658202 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:23.298485860 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1124] 1 False 11.54
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1124'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1124', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3658453 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9142s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:18.148181791 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_887] 1 False 22.82
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_887'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_887', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3658503 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8373s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:29.689897812 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1774] 1 False 12.83
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1774'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1774', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3658709 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2817s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:20.739152408 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1071] 1 False 13.84
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1071'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1071', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3658710 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6243s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:21.821875197 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1064] 1 False 9.45
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1064'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1064', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-41' pid=3659006 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:19.772618179 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-41: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_920] 1 False 14.91
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_920'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_920', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3659318 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7549s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7576s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:26.272119346 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1210] 1 False 15.15
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1210'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1210', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3659421 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3219s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:26.678484079 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1449] 1 False 13.15
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1449'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1449', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3659566 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4827s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1334] 1 False 11.43
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1334'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1334', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3660096 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2761s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2774s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:27.357800091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1920] 1 False 15.92
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1920'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1920', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3660316 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:34.146639292 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1651] 1 False 18.39
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1651'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1651', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3660840 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8336s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:37.994913839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1169] 1 False 16.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1169'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1169', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3661161 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4452s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:38.306289544 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_793] 1 False 10.18
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_793'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_793', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3661294 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:33.491444222 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1811] 1 False 12.47
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1811'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1811', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3661423 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:36.311480199 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1433] 1 False 16.87
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1433'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1433', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-44' pid=3661759 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.76336s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.76348s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.76353s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.76357s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.76365s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.76389s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.76399s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_706] 1 False 10.69
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_706'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_706', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-38' pid=3662300 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3470s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3482s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:37.120365892 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-38: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1922] 1 False 11.74
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1922'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1922', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3662402 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3655s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3664s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:38.438812577 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1756] 1 False 13.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1756'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1756', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3662564 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_739] 1 False 16.37
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_739'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_739', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3662677 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_890] 1 False 20.00
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_890'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_890', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3662798 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4121s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:48.112761090 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1653] 1 False 14.51
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1653'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1653', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3662859 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:43.098373106 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1506] 1 False 16.31
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1506'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1506', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3663128 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3179s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1354] 1 False 16.04
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1354'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1354', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-42' pid=3663740 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:49.904210351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1512] 1 False 22.54
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1512'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1512', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3663764 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9091s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_685] 1 False 10.82
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_685'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_685', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3663798 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3751s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:45.705611471 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1046] 1 False 9.56
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1046'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1046', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3664268 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:46.443063058 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1062] 1 False 15.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1062'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1062', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-39' pid=3664310 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:53.083770556 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-39: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_661] 1 False 16.54
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_661'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_661', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3664596 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5486s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:54.570987769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1442] 1 False 10.23
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1442'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1442', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3664651 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
munmap_chunk(): invalid pointer
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1199] 1 False 11.17
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1199'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1199', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3664675 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3846s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:49.661249121 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1557] 1 False 10.77
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1557'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1557', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-41' pid=3664779 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1431] 1 False 13.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1431'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1431', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-45' pid=3664893 parent=3536629 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.73088s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.73101s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.73106s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.73111s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.73118s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.73144s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.73158s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1477] 1 False 9.51
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1477'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1477', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-46' pid=3664992 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.254s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2157s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.47344s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.47351s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.47352s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.47354s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.47357s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.47365s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.47371s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1903] 1 False 15.09
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1903'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1903', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3665149 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:56.790969242 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1862] 1 False 13.62
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1862'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1862', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3665273 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8090s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8115s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:55.994978602 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1844] 1 False 19.60
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1844'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1844', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3665600 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3914s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3935s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:02.946253424 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_650] 1 False 9.21
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_650'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_650', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3665959 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:54.899132031 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1801] 1 False 17.17
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1801'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1801', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3665960 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:02.945770540 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_858] 1 False 19.24
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_858'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_858', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3666110 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3871s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:05.699606609 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1154] 1 False 14.39
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1154'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1154', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3666775 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:04.103162061 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1507] 1 False 14.13
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1507'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1507', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-43' pid=3666963 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1135] 1 False 9.15
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1135'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1135', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3667009 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.367s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3543s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3553s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:06:59.534336041 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1691] 1 False 8.97
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1691'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1691', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3667639 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:03.399442309 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1486] 1 False 14.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1486'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1486', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-47' pid=3667677 parent=3536268 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.127558s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.127589s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.127592s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.127596s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.127603s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.127628s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.127643s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_807] 1 False 20.05
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_807'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_807', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3667766 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3601s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:15.058870294 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_689] 1 False 14.47
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_689'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_689', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3667999 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6097s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:11.169017157 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1850] 1 False 14.69
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1850'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1850', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3668355 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8815s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:13.787989709 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1481] 1 False 17.61
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1481'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1481', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-46' pid=3668474 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1275] 1 False 13.50
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1275'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1275', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3668556 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4562s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4578s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:13.616212366 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1934] 1 False 23.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1934'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1934', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3669660 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:26.923481242 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1695] 1 False 22.88
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1695'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1695', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3669728 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:27.280406207 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1893] 1 False 13.73
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1893'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1893', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3669950 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4284s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:19.528510217 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1743] 1 False 9.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1743'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1743', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3670315 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6063s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1509] 1 False 13.57
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1509'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1509', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3670650 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6940s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6974s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_800] 1 False 13.62
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_800'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_800', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3670726 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5435s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5451s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:25.757399174 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1885] 1 False 9.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1885'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1885', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3671065 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4582s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:22.984122549 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1600] 1 False 13.22
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1600'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1600', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3671206 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9872s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9906s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:26.736990268 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1187] 1 False 17.04
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1187'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1187', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3671368 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:31.587916964 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1953] 1 False 19.89
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1953'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1953', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3671532 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3727s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:34.976944017 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_634] 1 False 16.97
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_634'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_634', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3671565 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9355s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:32.119133041 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1914] 1 False 22.27
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1914'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1914', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3671628 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.258s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2797s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:37.772191649 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1494] 1 False 12.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1494'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1494', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-48' pid=3671955 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1315] 1 False 10.65
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1315'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1315', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-47' pid=3672134 parent=3536424 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.780533s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.780556s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.780558s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.780560s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.780563s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.780573s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.780578s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.827145s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.827554s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.827572s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_937] 1 False 15.01
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_937'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_937', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3672183 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:32.443183837 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1833] 1 False 15.19
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1833'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1833', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-42' pid=3672245 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:32.899680831 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-42: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1877] 1 False 17.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1877'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1877', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3672439 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5857s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:36.029802922 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_679] 1 False 16.49
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_679'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_679', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3672604 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8646s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:35.994137481 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1108] 1 False 13.35
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1108'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1108', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3672633 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.456s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:33.192013877 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_710] 1 False 10.96
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3672904 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:32.850984019 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1325] 1 False 17.72
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1325'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1325', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-49' pid=3673477 parent=3536268 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9583s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.786275s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.786302s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.786303s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.786304s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.786307s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.786319s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.786325s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.832761s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.832809s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.832813s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1776] 1 False 12.74
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1776'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1776', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3673646 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3316s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:38.965749203 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_940] 1 False 13.36
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_940'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_940', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3674005 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:40.301638017 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1679] 1 False 19.47
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1679'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1679', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3674062 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:46.639058787 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1175] 1 False 16.60
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1175'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1175', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3674090 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3592s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3604s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:43.909128664 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1451] 1 False 11.42
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1451'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1451', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-48' pid=3674174 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3208s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
free(): invalid size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1558] 1 False 15.61
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1558'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1558', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3674204 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3613s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1532] 1 False 20.52
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1532'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1532', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3674749 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3843s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1286] 1 False 22.20
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1286'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1286', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-44' pid=3674897 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3741s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3755s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:54.717069965 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-44: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1685] 1 False 11.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1685'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1685', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-43' pid=3675039 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4001s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:44.154688071 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-43: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1434] 1 False 14.31
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1434'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1434', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-45' pid=3675463 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7467s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.96418s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.96440s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.96443s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.96448s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.96454s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.96478s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.96493s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1905] 1 False 21.58
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1905'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1905', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3675769 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8225s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:57.199520237 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1448] 1 False 8.57
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1448'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1448', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3675862 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.279s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2666s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1867] 1 False 10.96
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1867'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1867', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3675861 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4649s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:47.064982631 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1489] 1 False 19.98
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1489'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1489', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3676270 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_825] 1 False 21.43
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_825'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_825', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3676508 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.581s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9153s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:00.389280139 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_844] 1 False 12.64
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_844'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_844', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3676532 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.591s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9650s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:51.792651863 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1089] 1 False 15.62
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1089'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1089', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3676582 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8585s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8613s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:55.084577146 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1144] 1 False 14.59
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1144'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1144', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3676649 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.582s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:54.936913159 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_841] 1 False 13.56
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_841'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_841', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3676726 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:54.637812782 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1873] 1 False 8.94
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1873'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1873', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3677270 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4812s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4824s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:52.775943892 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1521] 1 False 21.76
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1521'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1521', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-46' pid=3677326 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1590] 1 False 19.93
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1590'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1590', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-44' pid=3677415 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3365s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:03.761901613 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. free(): corrupted unsorted chunks
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1720] 1 False 17.77
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1720'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1720', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3677441 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:02.156343001 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_809] 1 False 10.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_809'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_809', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3677828 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3695s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:57.849554406 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_672] 1 False 22.54
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_672'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_672', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3677981 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:10.246743327 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1708] 1 False 9.00
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1708'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1708', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3678010 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3645s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:07:57.029819561 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1699] 1 False 17.03
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1699'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1699', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3678015 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8584s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:05.075991270 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1793] 1 False 21.99
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1793'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1793', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3678169 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8730s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:10.515326574 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1818] 1 False 14.04
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1818'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1818', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3678247 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:03.353609449 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1278] 1 False 12.46
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1278'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1278', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3678540 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:04.272277839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_921] 1 False 17.05
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_921'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_921', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3678610 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8358s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8378s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:08.937141939 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1407] 1 False 9.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1407'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1407', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-50' pid=3678755 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.585s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10122s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.105565s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.105579s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.105582s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.105585s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.105591s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.105621s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.105634s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1614] 1 False 9.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1614'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1614', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-50' pid=3679250 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.73961s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.73973s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.73976s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.73978s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.73982s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.73990s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.73995s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1554] 1 False 9.22
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1554'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1554', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-45' pid=3679260 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1231] 1 False 12.58
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1231'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1231', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3679360 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:07.519725453 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1277] 1 False 13.52
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1277'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1277', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3679888 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9884s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:10.639411040 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1713] 1 False 22.64
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1713'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1713', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3679977 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2558s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2572s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:19.938605513 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1017] 1 False 9.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1017'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1017', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3680080 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:07.354786059 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1330] 1 False 16.67
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1330'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1330', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3680081 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8661s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:14.167598647 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1762] 1 False 10.80
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1762'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1762', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3680271 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1447] 1 False 8.79
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1447'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1447', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-51' pid=3680464 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8654s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.133770s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.133782s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.133786s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.133789s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.133794s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.133813s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.133827s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1748] 1 False 12.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1748'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1748', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3680529 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4586s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_734] 1 False 17.41
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3680769 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7619s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7642s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1341] 1 False 22.96
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1341'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1341', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3680940 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.603s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10095s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10125s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:26.275739615 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1804] 1 False 18.91
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1804'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1804', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3680977 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3073s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:22.934264419 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_878] 1 False 17.57
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_878'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_878', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-45' pid=3681004 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:21.687054462 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-45: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_892] 1 False 11.94
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_892'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_892', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3681051 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8987s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:16.203580108 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1949] 1 False 14.98
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1949'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1949', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3681174 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.597s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6280s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:20.120415748 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1461] 1 False 21.25
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1461'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1461', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3681709 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9825s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:28.266649526 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1281] 1 False 15.88
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1281'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1281', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3681742 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8394s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:23.506555199 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1007] 1 False 9.76
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1007'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1007', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3681801 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:17.752883659 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1225] 1 False 15.12
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1225'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1225', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3682018 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7764s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7788s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:24.112397685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_707] 1 False 11.74
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3682360 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9263s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:22.066937156 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1941] 1 False 12.06
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1941'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1941', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3682429 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.264s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2845s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:22.602503517 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1261] 1 False 22.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1261'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1261', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3682497 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5700s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:32.696328494 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1311] 1 False 11.67
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1311'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1311', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3682526 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8518s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:22.104974703 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_671] 1 False 14.15
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_671'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_671', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3682560 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4234s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:25.472153022 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1501] 1 False 14.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1501'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1501', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3682843 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6718s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6743s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1389] 1 False 8.66
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1389'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1389', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3683032 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.427s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7533s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.59958s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.59967s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.59968s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.59971s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.59974s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60035s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60042s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.111147s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.111215s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.111232s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1003] 1 False 20.00
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1003'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1003', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3683057 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:34.699077351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1262] 1 False 14.76
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1262'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1262', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3683487 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3327s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3340s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:32.667697889 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1436] 1 False 9.55
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1436'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1436', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3683703 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
double free or corruption (out)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1360] 1 False 11.13
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1360'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1360', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3683861 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:30.849229542 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1452] 1 False 20.71
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1452'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1452', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-48' pid=3684171 parent=3536280 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6971s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.139603s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.139629s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.139636s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.139640s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.139647s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.139670s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.139688s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1878] 1 False 15.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1878'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1878', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-46' pid=3684346 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4594s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:37.117008872 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-46: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1240] 1 False 17.40
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1240'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1240', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-49' pid=3684526 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:39.546451544 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-49: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1034] 1 False 8.91
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1034'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1034', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-47' pid=3684845 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:31.827822861 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-47: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1218] 1 False 16.35
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1218'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1218', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3684970 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4693s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4708s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:39.837680420 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1045] 1 False 13.63
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1045'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1045', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3685278 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.555s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9791s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:39.188079747 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1289] 1 False 12.16
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1289'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1289', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3685892 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4026s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:40.945075675 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1446] 1 False 18.42
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1446'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1446', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3685941 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6957s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1928] 1 False 18.32
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1928'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1928', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3686261 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:49.660424903 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_852] 1 False 9.68
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_852'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_852', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3686270 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.402s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4587s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:41.172037770 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1196] 1 False 22.26
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1196'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1196', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3686343 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:53.767754920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1900] 1 False 15.44
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1900'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1900', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3686504 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.605s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:47.334419499 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_777] 1 False 11.01
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_777'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_777', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3686707 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5709s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:43.418580452 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1297] 1 False 20.22
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1297'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1297', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3686819 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3705s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:53.552750906 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1399] 1 False 9.59
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1399'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1399', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3686952 parent=3536359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6569s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.102620s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.102655s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.102660s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.102664s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.102670s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.102702s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.102719s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1596] 1 False 10.85
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1596'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1596', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3687032 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:46.770313055 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1603] 1 False 17.54
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1603'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1603', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-47' pid=3687322 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3964s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:54.283285752 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_648] 1 False 13.92
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_648'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_648', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3687323 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3596s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:51.175400707 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1435] 1 False 12.16
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1435'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1435', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3687714 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1491] 1 False 12.98
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1491'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1491', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-50' pid=3687877 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1641] 1 False 11.50
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1641'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1641', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3688033 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3996s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:51.418797729 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_636] 1 False 15.99
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_636'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_636', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3688064 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6105s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:56.155313795 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1122] 1 False 23.61
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1122'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1122', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3688254 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8633s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:04.576476508 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1320] 1 False 12.11
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1320'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1320', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-54' pid=3688301 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1904] 1 False 10.76
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1904'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1904', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3688533 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4407s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:54.281758109 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1747] 1 False 18.92
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1747'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1747', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3688927 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4415s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1417] 1 False 14.73
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1417'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1417', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-49' pid=3688969 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.581s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.106172s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.106185s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.106189s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.106202s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.106209s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.106234s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.106252s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1910] 1 False 9.74
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1910'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1910', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3689303 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.617s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10721s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:08:56.939512050 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1450] 1 False 17.19
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1450'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1450', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-49' pid=3689822 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3877s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.60951s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60959s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60960s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60961s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60966s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60982s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60989s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1305] 1 False 12.09
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1305'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1305', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-53' pid=3690083 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.252358s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.252385s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.252389s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.252391s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.252395s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.252408s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.252414s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.300291s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.300594s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.300612s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1400] 1 False 22.68
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1400'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1400', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3690115 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1929] 1 False 10.03
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1929'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1929', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3690682 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3176s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3191s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:03.288706966 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1534] 1 False 10.85
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1534'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1534', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3690757 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1168] 1 False 12.40
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1168'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1168', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-48' pid=3691048 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4325s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:07.192673765 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-48: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1636] 1 False 14.96
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1636'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1636', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3691199 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10022s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10068s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:11.177362929 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1835] 1 False 16.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1835'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1835', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3691266 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7258s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:13.210642201 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1068] 1 False 9.34
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1068'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1068', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3691546 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:09.292057350 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1361] 1 False 12.41
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1361'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1361', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-55' pid=3691689 parent=3536268 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.225s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.41721s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.41733s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.41737s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.41740s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.41745s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.41773s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.41786s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.90195s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.90245s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.90257s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1529] 1 False 9.11
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1529'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1529', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-54' pid=3692181 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1269] 1 False 14.78
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1269'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1269', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3692352 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8231s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:18.116941946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1424] 1 False 11.37
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1424'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1424', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3692486 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4623s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1096] 1 False 18.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1096'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1096', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3692706 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3269s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3285s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:23.838355509 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1518] 1 False 17.07
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1518'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1518', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-49' pid=3692939 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_655] 1 False 19.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_655'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_655', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-50' pid=3693082 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7545s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:27.333005980 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-50: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1800] 1 False 11.77
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1800'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1800', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3693147 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:19.926715718 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1887] 1 False 10.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1887'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1887', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-51' pid=3693339 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:20.229220619 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-51: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1553] 1 False 9.87
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1553'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1553', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-52' pid=3693821 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4474s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1830] 1 False 12.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1830'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1830', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3693822 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:23.205353460 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1484] 1 False 14.67
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1484'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1484', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-52' pid=3694025 parent=3536289 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6856s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.136786s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.136805s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.136809s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.136811s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.136817s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.136844s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.136862s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1831] 1 False 19.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1831'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1831', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3694344 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:31.344026955 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1541] 1 False 9.70
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1541'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1541', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3694513 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7124s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7140s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1813] 1 False 20.20
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1813'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1813', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3694622 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3420s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:34.378607428 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1329] 1 False 18.47
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1329'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1329', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-57' pid=3694941 parent=3536629 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.90609s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.90634s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.90639s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.90643s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.90651s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.90677s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.90691s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.138856s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.138907s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.138916s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1359] 1 False 10.60
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1359'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1359', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3695390 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5939s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:30.127946370 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_663] 1 False 13.68
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_663'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_663', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3695445 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8133s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:34.090040345 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1701] 1 False 14.76
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1701'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1701', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3696258 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8540s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:38.730641346 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1027] 1 False 14.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1027'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1027', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3696284 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3733s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:38.644224348 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1535] 1 False 15.08
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1535'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1535', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-55' pid=3696546 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8589s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8616s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1022] 1 False 14.22
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1022'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1022', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3696631 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3367s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:40.038986394 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_850] 1 False 21.70
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_850'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_850', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3696724 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6917s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6936s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:47.811609580 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1190] 1 False 12.57
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1190'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1190', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3697040 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:40.361669148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_760] 1 False 12.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_760'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_760', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3697064 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_794] 1 False 22.95
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_794'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_794', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3697202 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:52.698282839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1937] 1 False 14.08
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1937'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1937', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3698200 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9257s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:48.070058036 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_922] 1 False 11.84
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_922'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_922', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3698284 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:46.296602506 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1527] 1 False 12.79
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1527'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1527', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-56' pid=3698624 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1326] 1 False 12.69
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1326'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1326', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-51' pid=3698676 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4107s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:49.392612950 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1245] 1 False 16.46
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1245'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1245', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3699163 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:55.212764927 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_698] 1 False 20.86
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_698'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_698', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3699250 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8648s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8673s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:00.049169662 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1631] 1 False 17.42
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1631'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1631', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3699675 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4146s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:57.880637818 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_948] 1 False 14.72
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_948'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_948', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3699724 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:55.350176893 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1670] 1 False 18.60
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1670'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1670', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3699970 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:01.023620347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1076] 1 False 12.55
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1076'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1076', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3700755 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4364s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:09:58.906277793 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1485] 1 False 20.41
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1485'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1485', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-54' pid=3700893 parent=3536460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8082s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.158468s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.158479s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.158482s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.158484s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.158489s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.158514s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.158526s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1349] 1 False 19.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1349'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1349', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-55' pid=3700911 parent=3536271 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9542s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.264616s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.264636s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.264639s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.264641s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.264644s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.264655s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.264661s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.311754s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.311849s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.311860s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1896] 1 False 14.47
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1896'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1896', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3701088 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5029s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:02.332458480 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1840] 1 False 16.17
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1840'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1840', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-53' pid=3701121 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3620s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:04.368787599 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-53: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_842] 1 False 16.76
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_842'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_842', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3701792 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4001s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:09.060189627 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1652] 1 False 14.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1652'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1652', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-52' pid=3701829 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.382s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7475s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7503s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:07.135378037 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-52: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1526] 1 False 9.84
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1526'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1526', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3701863 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_730] 1 False 9.08
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3702096 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9478s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1632] 1 False 13.47
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1632'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1632', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3702454 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:09.998803083 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_732] 1 False 14.93
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_732'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_732', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3702682 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9282s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1219] 1 False 8.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1219'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1219', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3702706 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2900s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:06.534492360 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1578] 1 False 14.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1578'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1578', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3702960 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1092] 1 False 22.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1092'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1092', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3703327 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11545s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11574s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:22.536316974 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1395] 1 False 11.16
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1395'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1395', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-58' pid=3703698 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.47s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:12.903904609 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1002] 1 False 16.92
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1002'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1002', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3703747 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:19.303098428 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_802] 1 False 11.70
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_802'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_802', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3703783 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8501s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:14.345507633 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1412] 1 False 15.17
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1412'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1412', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-57' pid=3703786 parent=3536831 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.39437s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.39448s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.39450s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.39452s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.39457s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.39468s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.39474s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1492] 1 False 17.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1492'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1492', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3704069 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.43s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7460s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_813] 1 False 22.80
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_813'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_813', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3704205 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4750s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.11918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.13226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.13296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.13361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.16723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.17273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.17356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.17525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.17622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.17696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.17766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.17835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.17916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.18011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.18062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.18126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.18211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.18279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.18360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.18468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.18561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.18654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.18747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.18815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.18873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.18956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.19037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.19120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.19126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.19158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:26.841515467 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1156] 1 False 10.74
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1156'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1156', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3704305 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8689s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8711s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:15.124046873 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1597] 1 False 10.81
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1597'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1597', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-58' pid=3704329 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9118s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9149s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.141198s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.141213s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.141216s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.141220s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.141225s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.141256s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.141273s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:15.088522462 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1917] 1 False 18.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1917'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1917', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3704773 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6695s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6718s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:24.516849928 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_792] 1 False 16.23
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_792'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_792', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3704928 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3994s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:22.767443960 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1110] 1 False 10.13
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1110'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1110', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3704961 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:16.819502781 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1572] 1 False 18.70
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1572'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1572', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-53' pid=3705001 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1876] 1 False 20.62
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1876'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1876', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3705002 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.535s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8821s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:27.856445390 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1176] 1 False 18.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1176'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1176', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3705229 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8348s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:27.796276826 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1942] 1 False 12.10
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1942'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1942', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3705746 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7489s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:24.762865359 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1420] 1 False 10.95
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1420'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1420', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-59' pid=3705911 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3026s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.64264s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.64288s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.64291s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.64293s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.64300s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.64327s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.64344s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1812] 1 False 20.84
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1812'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1812', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3705995 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10268s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:34.680640817 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_956] 1 False 10.66
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_956'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_956', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3706134 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3479s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:25.076132558 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_910] 1 False 20.14
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_910'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_910', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3706302 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:35.272053249 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_656] 1 False 15.41
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_656'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_656', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-54' pid=3706480 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.10434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12453s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:31.589495030 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-54: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1909] 1 False 16.06
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1909'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1909', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3707010 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:37.207072881 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1815] 1 False 12.71
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1815'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1815', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3707181 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3834s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3863s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:34.509019869 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1139] 1 False 15.37
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1139'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1139', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3707394 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3342s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:37.999831182 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1837] 1 False 9.79
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1837'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1837', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3707843 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:33.713754319 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1559] 1 False 12.12
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1559'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1559', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3707997 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6539s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1054] 1 False 21.94
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1054'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1054', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3708001 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.576s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8763s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:46.235577007 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1926] 1 False 13.44
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1926'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1926', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3708092 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3943s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:38.003701260 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1619] 1 False 9.01
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1619'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1619', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3708156 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5690s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1936] 1 False 22.99
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1936'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1936', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3708302 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:48.075282928 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1635] 1 False 13.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1635'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1635', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3708418 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7494s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7519s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:39.141859114 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_838] 1 False 19.76
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_838'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_838', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3708692 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:46.750213250 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_669] 1 False 15.47
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_669'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_669', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3708885 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3523s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:43.388868810 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_654] 1 False 13.31
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_654'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_654', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3709124 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:42.812883796 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_761] 1 False 11.11
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_761'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_761', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3709552 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.262s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9085s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1911] 1 False 9.92
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1911'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1911', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3709614 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.364s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:43.729445350 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_733] 1 False 8.87
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_733'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_733', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-57' pid=3709763 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1474] 1 False 10.49
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1474'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1474', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-59' pid=3709810 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.298s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3349s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.62692s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.62703s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.62705s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.62709s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.62712s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.62725s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.62730s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_924] 1 False 10.87
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_924'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_924', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3710505 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2784s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:48.039602477 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1131] 1 False 15.89
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1131'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1131', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3710810 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:53.477936301 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1121] 1 False 19.40
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1121'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1121', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-55' pid=3710845 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8999s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:57.019006805 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-55: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1754] 1 False 16.81
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1754'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1754', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3711003 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8923s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_767] 1 False 19.50
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_767'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_767', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3711027 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.558s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9162s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9186s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1150] 1 False 23.48
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1150'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1150', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3711028 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4698s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:01.506554707 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1432] 1 False 16.06
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1432'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1432', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3711080 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.230s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:53.773092709 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis free(): corrupted unsorted chunks
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1458] 1 False 14.07
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1458'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1458', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3711081 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8713s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8742s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1363] 1 False 18.30
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1363'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1363', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-59' pid=3711256 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:56.988923548 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1318] 1 False 11.59
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1318'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1318', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3711603 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4389s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4406s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1164] 1 False 9.83
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1164'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1164', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3711706 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.240s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3356s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:53.256593785 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1829] 1 False 11.87
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1829'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1829', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3711707 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8213s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:10:55.313502288 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1814] 1 False 19.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1814'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1814', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3711764 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4345s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:03.233978286 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1723] 1 False 14.77
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1723'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1723', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3712040 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5884s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:00.014206153 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1948] 1 False 16.38
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1948'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1948', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3712251 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9501s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:02.663954849 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_642] 1 False 17.57
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_642'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_642', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3712295 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:04.082282451 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1583] 1 False 16.92
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1583'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1583', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3712427 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1236] 1 False 13.84
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1236'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1236', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3712664 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:01.917102635 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_756] 1 False 10.52
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_756'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_756', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3712921 parent=3536359 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3875s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1443] 1 False 12.84
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1443'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1443', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-63' pid=3713234 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3624s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3635s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1956] 1 False 14.02
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1956'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1956', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3713426 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8864s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:06.900591101 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1052] 1 False 18.40
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1052'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1052', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-59' pid=3713531 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10817s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:11.677923965 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-59: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1621] 1 False 16.22
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1621'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1621', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3713662 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:09.401891526 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1408] 1 False 12.80
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1408'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1408', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-63' pid=3713803 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_629] 1 False 13.42
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_629'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_629', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3713910 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.553s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:08.153118534 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1296] 1 False 22.31
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1296'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1296', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3714030 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.584s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12118s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:17.702122217 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1623] 1 False 17.69
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1623'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1623', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-57' pid=3714077 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3033s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:13.420600275 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1871] 1 False 12.11
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1871'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1871', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-56' pid=3714262 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.43s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8841s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:09.156413151 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-56: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1185] 1 False 23.92
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1185'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1185', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3714667 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.581s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:23.550207813 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1058] 1 False 11.01
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1058'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1058', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3715081 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4395s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:12.334206322 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1328] 1 False 16.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1328'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1328', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3715146 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9857s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.396133s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.396154s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.396156s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.396158s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.396162s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.396173s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.396177s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.443362s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.443435s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.443445s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1807] 1 False 18.88
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1807'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1807', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3715280 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:20.874952626 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_705] 1 False 15.65
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_705'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_705', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3715339 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:17.924684895 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1376] 1 False 15.37
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1376'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1376', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-61' pid=3715646 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6760s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.62255s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.62271s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.62275s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.62278s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.62286s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.62315s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.62331s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.109891s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.110014s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.110029s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1304] 1 False 14.20
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1304'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1304', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3715686 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5930s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:17.899785866 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1716] 1 False 23.54
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1716'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1716', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3716257 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:30.494404946 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1611] 1 False 21.19
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1611'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1611', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3716281 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7763s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:28.015835213 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1710] 1 False 10.50
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1710'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1710', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-57' pid=3716603 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:19.735530810 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-57: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1648] 1 False 19.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1648'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1648', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3716781 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:30.021132950 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1345] 1 False 15.69
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1345'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1345', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-60' pid=3717031 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.808423s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.808464s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.808467s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.808470s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.808475s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.808500s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.808509s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.855784s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.855878s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.855889s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1945] 1 False 9.10
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1945'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1945', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3717164 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5201s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:21.449400222 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1479] 1 False 14.38
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1479'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1479', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-66' pid=3717382 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3297s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.64645s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.64658s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.64661s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.64666s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.64670s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.64695s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.64710s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1609] 1 False 8.71
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1609'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1609', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3717455 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3704s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:22.215482754 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1620] 1 False 17.50
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1620'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1620', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3717593 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.567s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9021s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_695] 1 False 10.96
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_695'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_695', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3718075 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7925s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:28.300068176 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1157] 1 False 23.78
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1157'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1157', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3718199 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10279s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10304s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:41.686470143 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1380] 1 False 17.94
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1380'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1380', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3718226 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:35.561766209 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_797] 1 False 20.13
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_797'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_797', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-58' pid=3718629 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7109s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:39.911281667 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-58: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1761] 1 False 13.13
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1761'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1761', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-64' pid=3718844 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.72456s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.72468s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.72473s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.72476s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.72481s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.72505s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.72515s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1402] 1 False 16.14
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1402'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1402', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3718929 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.70629s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.70659s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.70662s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.70665s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.70670s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.70684s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.70692s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1319] 1 False 15.41
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1319'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1319', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-58' pid=3718930 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.757811s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.757856s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.757859s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.757872s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.757880s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.757904s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.757917s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.805963s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.806086s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.806098s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1291] 1 False 21.48
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1291'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1291', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3719055 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.207s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2365s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:42.992282396 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_929] 1 False 14.66
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_929'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_929', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3719352 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.642s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:37.578284169 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1500] 1 False 20.52
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1500'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1500', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3719455 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4688s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1545] 1 False 20.78
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1545'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1545', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-64' pid=3719667 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7435s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_717] 1 False 9.59
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-60' pid=3720098 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8557s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:36.951271470 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-60: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1166] 1 False 22.24
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1166'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1166', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3720386 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:50.586762668 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1249] 1 False 11.78
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1249'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1249', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3720443 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4054s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:40.380526683 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1562] 1 False 13.81
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1562'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1562', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3720725 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1598] 1 False 12.62
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1598'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1598', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-59' pid=3720842 parent=3536280 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.135953s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.135987s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.135990s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.135993s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.135999s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.136030s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.136044s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1663] 1 False 10.64
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1663'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1663', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3721026 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3096s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:43.513299297 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_952] 1 False 15.37
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_952'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_952', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3721106 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8962s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:48.677103528 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1633] 1 False 19.85
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1633'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1633', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3721135 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8747s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:53.573429686 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1465] 1 False 21.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1465'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1465', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-65' pid=3721603 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8308s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration ********** 0.139329s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.139350s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.139353s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.139356s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.139362s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.139383s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.139398s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1177] 1 False 10.30
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1177'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1177', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3722016 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4475s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:47.824534125 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_637] 1 False 14.44
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_637'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_637', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3722580 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.376s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:54.825176452 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1134] 1 False 21.16
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1134'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1134', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3722629 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.398s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4513s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:01.853162995 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1024] 1 False 22.82
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1024'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1024', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3722811 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:04.599779677 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_652] 1 False 17.99
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_652'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_652', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3723046 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7640s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7669s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:00.715410940 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1332] 1 False 23.18
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1332'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1332', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-60' pid=3723335 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6695s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:06.321225145 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1798] 1 False 21.81
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1798'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1798', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3723369 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8083s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8111s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:05.794835975 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_812] 1 False 9.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_812'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_812', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3723765 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6234s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:56.961694215 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1634] 1 False 11.42
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1634'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1634', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3723844 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:11:59.252125373 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1414] 1 False 13.64
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1414'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1414', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-64' pid=3724095 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.75433s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.75443s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.75446s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.75448s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.75453s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.75465s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.75470s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1482] 1 False 9.32
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1482'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1482', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-60' pid=3724319 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.397s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5051s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5064s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.74727s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.74742s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.74747s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.74751s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.74757s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.74787s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.74801s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_864] 1 False 18.02
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_864'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_864', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3724510 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4119s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:07.660196806 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1588] 1 False 18.69
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1588'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1588', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-66' pid=3724799 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.577s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9356s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9386s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:08.841839922 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_862] 1 False 16.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_862'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_862', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3725190 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5482s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5500s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:10.363105810 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_955] 1 False 11.00
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_955'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_955', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3725340 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8494s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:05.934875299 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1496] 1 False 10.67
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1496'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1496', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-65' pid=3725756 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1715s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.9897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.10154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.10251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.10361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.10517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.10576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.10652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.10712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.10759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.10810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.10905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.10974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.11033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.11090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.11167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.11222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.11283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.11365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1890] 1 False 14.81
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1890'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1890', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3725759 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3913s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:11.969029016 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_927] 1 False 15.88
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_927'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_927', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3725869 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4187s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:13.396181730 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1078] 1 False 14.28
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1078'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1078', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3725985 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.611s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10621s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:12.998423767 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1013] 1 False 10.25
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1013'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1013', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3726082 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4386s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:09.597599410 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1105] 1 False 12.82
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1105'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1105', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3726349 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.741s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:14.697236428 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_870] 1 False 21.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_870'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_870', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3726765 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:24.461367918 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1734] 1 False 11.50
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1734'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1734', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-65' pid=3726923 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.405s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.59089s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.59097s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.59099s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.59101s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.59102s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.59116s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.59123s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_640] 1 False 11.44
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_640'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_640', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3727017 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:15.521688926 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_876] 1 False 21.06
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_876'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_876', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3727232 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9276s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:25.739491288 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1385] 1 False 20.10
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1385'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1385', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3727601 parent=3536268 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.54787s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.54801s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.54807s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.54811s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.54818s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.54842s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.54854s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.101270s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.101351s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.101373s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1237] 1 False 12.01
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1237'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1237', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3727659 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3793s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:17.965482179 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1550] 1 False 13.22
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1550'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1550', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-61' pid=3727819 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4265s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_946] 1 False 15.36
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_946'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_946', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3727979 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8556s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:23.018375786 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1032] 1 False 9.85
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1032'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1032', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-63' pid=3728105 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:18.070219347 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-63: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_916] 1 False 12.50
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_916'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_916', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3728289 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4466s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4483s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:21.861831355 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1019] 1 False 20.03
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1019'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1019', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3728315 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.853s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5816s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:29.597937729 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1366] 1 False 14.00
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1366'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1366', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-62' pid=3728862 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.365s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6646s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6666s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:26.737865012 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1935] 1 False 11.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1935'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1935', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3728970 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3890s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:24.807171247 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1690] 1 False 16.56
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1690'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1690', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-61' pid=3729148 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9091s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9116s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:30.631206351 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-61: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1726] 1 False 8.78
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1726'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1726', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-66' pid=3729218 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3729s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3745s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.35370s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.35388s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.35391s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.35394s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.35402s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.35426s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.35436s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1473] 1 False 10.61
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1473'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1473', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-68' pid=3729450 parent=3536424 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9090s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.129405s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.129419s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.129425s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.129427s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.129435s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.129459s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.129474s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1698] 1 False 16.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1698'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1698', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3729554 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:32.021176937 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_688] 1 False 14.06
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_688'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_688', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3729618 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:29.310326910 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1453] 1 False 16.50
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1453'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1453', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3729644 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4748s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1123] 1 False 15.51
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1123'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1123', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3729650 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4956s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:31.110513005 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1206] 1 False 16.05
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1206'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1206', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3730395 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8843s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:37.690802842 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1714] 1 False 21.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3730474 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2780s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:43.317794293 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1919] 1 False 10.85
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1919'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1919', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3730659 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4103s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4120s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:33.946249515 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1335] 1 False 14.14
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1335'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1335', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-67' pid=3730960 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7053s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7067s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.395335s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.395368s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.395374s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.395376s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.395383s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.395405s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.395418s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.460239s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.460396s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.460412s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_785] 1 False 17.95
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_785'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_785', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3731054 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4337s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:42.866735403 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1313] 1 False 15.40
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1313'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1313', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-67' pid=3731303 parent=3536285 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4432s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.755577s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.755607s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.755609s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.755611s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.755615s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.755626s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.755632s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.803655s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.804017s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.804036s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1564] 1 False 17.33
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1564'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1564', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3731338 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3120s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3134s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1464] 1 False 15.25
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1464'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1464', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-67' pid=3731422 parent=3536359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3784s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.60583s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60594s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60597s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60601s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60605s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60620s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60632s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1316] 1 False 15.84
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1316'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1316', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-67' pid=3731613 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4416s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4436s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_889] 1 False 9.36
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_889'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_889', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3732045 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4868s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4890s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:38.704180398 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_880] 1 False 17.80
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_880'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_880', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3732133 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4486s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4495s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:47.455381915 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1189] 1 False 17.76
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1189'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1189', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-62' pid=3732293 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10009s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:48.406605422 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-62: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1141] 1 False 16.75
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1141'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1141', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3732390 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4214s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:47.919424253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_833] 1 False 12.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_833'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_833', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3732590 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4658s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:44.195609083 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_765] 1 False 8.86
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_765'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_765', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-68' pid=3732591 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9404s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1759] 1 False 14.47
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1759'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1759', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3732923 parent=3536280 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3287s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.26500s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.26506s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.26508s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.26509s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.26514s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.26527s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.26532s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1222] 1 False 15.77
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1222'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1222', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3733285 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:51.946775966 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1717] 1 False 19.99
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1717'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1717', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3733588 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8923s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:57.738586125 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1265] 1 False 20.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1265'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1265', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3733806 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6632s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:59.095031619 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1194] 1 False 16.26
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1194'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1194', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3733830 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:55.041583612 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_696] 1 False 16.88
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_696'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_696', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-64' pid=3733884 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:56.156844284 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-64: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1797] 1 False 11.21
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1797'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1797', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3734199 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4926s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:52.484097205 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_925] 1 False 18.23
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_925'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_925', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3734251 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:59.827663492 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1771] 1 False 15.86
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1771'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1771', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-69' pid=3734672 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7325s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.66727s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.66738s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.66740s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.66743s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.66748s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.66776s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.66790s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_795] 1 False 13.21
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_795'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_795', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3734924 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4696s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4707s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:57.546547148 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1817] 1 False 9.17
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1817'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1817', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3735292 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:55.025265966 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_718] 1 False 17.00
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3735345 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:03.278102156 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1273] 1 False 10.57
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1273'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1273', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3735592 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:12:58.083306905 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1718] 1 False 18.98
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1718'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1718', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3735725 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6168s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:06.845996714 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1348] 1 False 10.45
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1348'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1348', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-63' pid=3735823 parent=3536664 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6491s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 1.413259s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 1.413309s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 1.413313s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 1.413318s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 1.413326s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 1.413355s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 1.413374s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 1.461027s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 1.461116s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 1.461134s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1671] 1 False 15.61
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1671'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1671', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3735985 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:05.180646794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1375] 1 False 21.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1375'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1375', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3736068 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.89s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.90s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6732s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:11.783143033 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1214] 1 False 10.97
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1214'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1214', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3736334 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:03.412786539 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1531] 1 False 14.73
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1531'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1531', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3737076 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9397s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_805] 1 False 9.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_805'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_805', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3737573 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3954s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:06.753648811 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1397] 1 False 20.77
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1397'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1397', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3737652 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3714s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_725] 1 False 16.92
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_725'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_725', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3737996 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5156s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1791] 1 False 14.32
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1791'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1791', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3738144 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:14.232276806 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_776] 1 False 15.74
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_776'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_776', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3738488 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3086s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:16.830002894 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1940] 1 False 15.98
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1940'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1940', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3738697 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7551s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:17.974073025 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1898] 1 False 22.44
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1898'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1898', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3738963 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3957s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3972s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:25.794793714 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1560] 1 False 15.20
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1560'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1560', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3739175 parent=3536831 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3006s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1668] 1 False 13.20
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1668'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1668', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3739400 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:19.062382876 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1780] 1 False 10.29
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1780'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1780', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3739628 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4462s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:17.108765910 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1638] 1 False 15.46
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1638'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1638', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3739629 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:22.371143589 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1101] 1 False 20.90
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1101'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1101', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3739740 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3813s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:30.137830204 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1109] 1 False 15.86
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1109'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1109', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3740126 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.248s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:26.668633838 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1216] 1 False 12.65
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1216'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1216', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-65' pid=3740240 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:23.990222828 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-65: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1146] 1 False 14.18
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1146'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1146', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3740295 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8949s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8977s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:25.636910718 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1162] 1 False 13.18
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1162'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1162', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3740449 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.614s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:25.412117810 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1828] 1 False 20.36
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1828'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1828', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3740698 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3981s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:34.626355637 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1727] 1 False 9.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1727'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1727', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-71' pid=3740978 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4766s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1792] 1 False 22.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1792'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1792', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3741358 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:39.208599359 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_796] 1 False 18.97
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_796'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_796', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3741407 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7438s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:35.936693561 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1035] 1 False 8.91
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1035'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1035', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3741484 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2981s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2998s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:26.079728087 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_942] 1 False 16.18
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_942'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_942', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3741581 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.429s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6433s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:33.568283120 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1207] 1 False 17.73
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1207'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1207', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-66' pid=3741727 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:35.816029902 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-66: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_773] 1 False 17.59
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_773'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_773', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3742044 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3199s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:36.672597253 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1192] 1 False 19.27
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1192'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1192', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3742068 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:38.494356920 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_917] 1 False 17.11
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_917'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_917', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3742099 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3127s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:36.545125236 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1629] 1 False 12.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1629'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1629', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-71' pid=3742263 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4458s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.123036s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.123052s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.123055s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.123058s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.123063s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.123086s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.123097s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1350] 1 False 9.29
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1350'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1350', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-71' pid=3742555 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3770s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.26843s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.26850s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.26851s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.26852s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.26857s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.26869s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.26876s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.73863s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.73928s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.73940s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1707] 1 False 14.99
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1707'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1707', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3742960 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7811s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:40.089216599 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1584] 1 False 15.39
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1584'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1584', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3743199 parent=3536730 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4040s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - -1107064492. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:40.423563048 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1499] 1 False 13.15
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1499'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1499', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3743252 parent=3536765 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.605s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1773] 1 False 16.95
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1773'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1773', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3743295 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7763s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:42.760848956 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1927] 1 False 15.64
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1927'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1927', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3743365 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.77s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.78s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.424s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:41.749245806 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1809] 1 False 11.76
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1809'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1809', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3743412 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:38.541194200 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1224] 1 False 10.34
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1224'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1224', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3744012 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3766s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:41.851041261 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1745] 1 False 19.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1745'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1745', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3744092 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1958] 1 False 14.47
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1958'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1958', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3744312 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:46.871991996 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1843] 1 False 21.57
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1843'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1843', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3744333 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2931s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:54.002693827 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1528] 1 False 22.82
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1528'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1528', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3744384 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4076s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1445] 1 False 14.82
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1445'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1445', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-72' pid=3744507 parent=3537186 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4254s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.115372s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.115387s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.115391s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.115394s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.115399s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.115428s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.115440s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_860] 1 False 14.25
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_860'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_860', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3744603 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6473s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6500s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:47.846235091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_693] 1 False 12.97
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_693'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_693', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3744740 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:47.428392367 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1280] 1 False 17.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1280'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1280', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-67' pid=3745122 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:53.176995042 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-67: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1573] 1 False 18.31
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1573'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1573', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3745184 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8367s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1566] 1 False 21.33
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1566'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1566', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3745300 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7966s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7991s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1401] 1 False 13.81
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1401'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1401', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-71' pid=3745669 parent=3536493 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3439s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3455s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1688] 1 False 13.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1688'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1688', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3745684 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3154s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:52.316821909 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1371] 1 False 10.08
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1371'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1371', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-75' pid=3745797 parent=3536765 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.375s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.41693s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.41703s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.41707s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.41709s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.41711s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.41726s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.41733s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.89571s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.89614s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.89632s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1183] 1 False 20.64
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1183'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1183', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3745880 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:59.917623828 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1826] 1 False 11.28
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1826'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1826', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3746358 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10093s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:52.081774772 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1888] 1 False 10.03
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1888'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1888', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3746368 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5999s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:50.811830822 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_784] 1 False 11.84
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_784'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_784', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3746451 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:52.742163676 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1272] 1 False 16.29
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1272'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1272', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3746650 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7860s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:13:57.978791685 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1552] 1 False 12.70
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1552'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1552', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-68' pid=3746791 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1051] 1 False 12.88
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1051'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1051', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-68' pid=3747207 parent=3536664 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9189s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9215s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:00.354580438 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-68: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1317] 1 False 16.32
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1317'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1317', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3748041 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8587s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8622s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:08.219191119 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1575] 1 False 13.83
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1575'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1575', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3748388 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4798s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4808s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1846] 1 False 17.46
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1846'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1846', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3748669 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:12.872197053 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1692] 1 False 10.07
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1692'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1692', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3748725 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:05.683525769 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1880] 1 False 17.69
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1880'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1880', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3749097 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.738s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11477s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11507s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:14.777023735 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1173] 1 False 12.80
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1173'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1173', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3749319 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:10.703675890 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1323] 1 False 13.75
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1323'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1323', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-69' pid=3749343 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.373s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6278s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1370] 1 False 19.13
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1370'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1370', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3749383 parent=3536277 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8132s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:16.723701619 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1148] 1 False 15.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1148'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1148', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3750704 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5768s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5783s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:20.978971263 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1735] 1 False 20.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1735'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1735', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3750752 parent=3536268 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5067s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_766] 1 False 10.83
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_766'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_766', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3750941 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3895s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1581] 1 False 9.87
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1581'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1581', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3751205 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3138s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1346] 1 False 14.73
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1346'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1346', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3751383 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.354s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4008s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:23.962917239 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1696] 1 False 16.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1696'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1696', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-73' pid=3751537 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8729s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:26.371849953 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-73: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1284] 1 False 19.72
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1284'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1284', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3751675 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4688s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:30.444563200 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1459] 1 False 8.95
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1459'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1459', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-70' pid=3751987 parent=3537059 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4413s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:20.299005269 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1785] 1 False 17.30
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1785'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1785', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3752329 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7922s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:30.040807258 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1441] 1 False 17.64
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1441'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1441', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3752360 parent=3536629 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3637s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.68658s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.68671s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.68674s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.68678s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.68683s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.68708s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.68721s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1738] 1 False 9.92
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1738'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1738', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3752486 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.360s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4609s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1640] 1 False 12.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1640'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1640', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-69' pid=3752934 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3065s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:28.131213651 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-69: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1382] 1 False 16.88
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1382'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1382', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3752966 parent=3536324 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8870s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8900s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name [TIDL Import] [PARSER] ERROR: Input ONNX tensor element type - 0. Only FLOAT, UINT8, INT32 and INT64 inputs supported for ONNX runtime -- [tidl_onnxRtImport_EP.cpp, 1861] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_subgraphImport -- [tidl_onnxRtImport_EP.cpp, 1950] [TIDL Import] [PARSER] ERROR: - Failed in function: TIDL_computeInvokeFunc -- [tidl_onnxRtImport_EP.cpp, 2753]
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:32.516368008 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running TIDL_0 node. Name:'TIDLExecutionProvider_TIDL_0_0' Status Message: TIDL Compute Invoke Failed. terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_798] 1 False 9.37
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_798'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_798', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3753099 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3060s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:26.649292456 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1266] 1 False 14.99
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1266'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1266', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3753289 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7692s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:32.997552916 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1369] 1 False 11.72
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1369'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1369', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3753484 parent=3536265 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3882s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.27862s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.27870s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.27872s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.27874s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.27878s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.27890s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.27897s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.76573s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.76683s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.76705s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_772] 1 False 11.62
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_772'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_772', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3753709 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:31.628034451 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1789] 1 False 20.30
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1789'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1789', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-71' pid=3753793 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9855s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9880s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:41.093403794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0] Process Process-71: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 1 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1861] 1 False 10.42
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1861'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1861', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3753968 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8778s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:33.819888651 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1579] 1 False 9.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1579'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1579', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-75' pid=3754102 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5969s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_632] 1 False 22.44
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_632'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_632', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3754325 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6858s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:47.906403839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1158] 1 False 15.61
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1158'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1158', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3754643 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6699s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6725s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:42.095671991 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1423] 1 False 11.54
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1423'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1423', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-75' pid=3754698 parent=3536277 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5772s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5792s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.88545s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.88561s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.88566s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.88569s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.88574s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.88599s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.88614s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1255] 1 False 9.43
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1255'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1255', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-70' pid=3754883 parent=3536280 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:37.688571518 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-70: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1290] 1 False 10.61
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1290'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1290', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3755120 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:39.635441078 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_754] 1 False 19.80
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_754'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_754', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-74' pid=3755121 parent=3536289 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_932] 1 False 15.28
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_932'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_932', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3755389 parent=3536271 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:45.401491701 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1551] 1 False 13.50
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1551'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1551', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3755517 parent=3536265 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7498s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7516s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1472] 1 False 17.67
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1472'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1472', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3755541 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4396s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1438] 1 False 13.12
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1438'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1438', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3755545 parent=3536629 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.274s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2782s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:43.346626059 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1697] 1 False 12.23
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1697'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1697', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3755866 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.269s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5131s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5139s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:43.896515128 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1848] 1 False 16.83
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1848'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1848', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3755890 parent=3536962 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5735s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5751s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:48.733355853 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_853] 1 False 20.19
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_853'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_853', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3756174 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.593s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:53.249199208 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1661] 1 False 12.70
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1661'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1661', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3756177 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11335s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:45.780323657 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1891] 1 False 15.48
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1891'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1891', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3756416 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.498s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9240s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:49.699408257 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1517] 1 False 9.29
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1517'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1517', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-77' pid=3756526 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1952] 1 False 20.23
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1952'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1952', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3757046 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.564s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:58.368048868 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1795] 1 False 16.93
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1795'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1795', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3757090 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1095s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:55.260820839 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1247] 1 False 10.66
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1247'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1247', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-72' pid=3757370 parent=3537059 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:51.815482738 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-72: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1863] 1 False 11.99
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1863'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1863', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3757602 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:54.099948317 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_736] 1 False 16.37
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_736'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_736', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-72' pid=3757677 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9702s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1074690309 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1646] 1 False 12.30
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1646'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1646', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3757962 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5773s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5795s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:55.806502861 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1115] 1 False 13.74
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1115'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1115', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3758000 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3286s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:57.568172105 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_939] 1 False 17.93
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_939'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_939', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3758073 parent=3536559 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4083s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:01.926909975 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_919] 1 False 9.76
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_919'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_919', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3758128 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.597s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:53.956028997 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1556] 1 False 16.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1556'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1556', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3758443 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_843] 1 False 21.13
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_843'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_843', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3758553 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3490s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3508s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:06.923207388 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_914] 1 False 18.24
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_914'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_914', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3758586 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.517s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7458s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7489s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:04.308619536 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1520] 1 False 16.10
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1520'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1520', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3758587 parent=3537186 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5270s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1944] 1 False 10.20
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1944'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1944', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3758987 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5381s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:14:58.425992383 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1392] 1 False 22.73
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1392'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1392', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3759164 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.857s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10834s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.77053s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.77064s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.77067s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.77070s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.77079s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.77104s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.77120s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.124852s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.125030s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.125043s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_831] 1 False 18.84
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_831'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_831', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3759177 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:07.723009150 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1626] 1 False 16.08
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1626'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1626', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3759307 parent=3536928 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7593s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.118337s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.118386s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.118394s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.118398s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.118405s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.118426s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.118437s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1508] 1 False 11.04
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1508'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1508', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3759860 parent=3536424 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.451s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10496s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10532s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_714] 1 False 10.20
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_714'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_714', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3759884 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.386s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:04.346594636 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1113] 1 False 14.64
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1113'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1113', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3760106 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:09.946711366 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1421] 1 False 17.24
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1421'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1421', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3760189 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.426s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8699s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1067578608 Running inference - currFrameIdx > numFramesCalibration ********** 0.85559s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.85577s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.85583s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.85587s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.85593s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.85622s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.85635s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1709] 1 False 17.16
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1709'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1709', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3760288 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10938s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10966s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:13.641052091 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1467] 1 False 14.61
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1467'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1467', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3760616 parent=3536359 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.69934s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.69941s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.69943s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.69945s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.69948s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.69965s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.69973s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1403] 1 False 9.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1403'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1403', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3761014 parent=3536460 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:07.202120616 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1825] 1 False 11.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1825'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1825', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3761029 parent=3536274 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4668s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:09.841920998 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1537] 1 False 18.24
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1537'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1537', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3761170 parent=3536664 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3218s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1107] 1 False 12.55
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1107'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1107', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3761249 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:12.153773471 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -2 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1427] 1 False 14.43
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1427'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1427', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-78' pid=3761485 parent=3536559 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4804s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4817s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration ********** 0.46020s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.46044s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.46047s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.46050s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.46053s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.46065s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.46069s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_681] 1 False 12.52
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_681'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_681', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3761542 parent=3537186 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:14.783694277 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_865] 1 False 14.85
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_865'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_865', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3761830 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4086s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4098s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:19.254933177 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_674] 1 False 15.20
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_674'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_674', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3762115 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.417s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5217s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:21.142803132 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1413] 1 False 19.06
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1413'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1413', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3762267 parent=3536562 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.13937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.14310s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1344] 1 False 10.56
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1344'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1344', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-78' pid=3762457 parent=3536324 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9606s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.896699s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.896743s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.896748s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.896751s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.896757s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.896786s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.896802s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.944398s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.944529s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.944545s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_881] 1 False 17.19
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_881'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_881', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3762466 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:24.301413800 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1819] 1 False 15.83
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1819'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1819', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-74' pid=3762610 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:23.474534731 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-74: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_872] 1 False 17.87
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_872'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_872', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3762677 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:25.708872590 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_728] 1 False 18.84
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_728'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_728', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-80' pid=3763178 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.358s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4539s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_646] 1 False 11.62
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_646'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_646', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3763208 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.433s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7598s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:21.650097509 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1681] 1 False 9.32
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1681'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1681', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3763245 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4372s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4391s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:19.601634218 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1585] 1 False 12.76
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1585'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1585', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3763460 parent=3536962 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9089s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration ********** 0.106060s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.106071s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.106075s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.106078s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.106083s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.106107s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.106124s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1347] 1 False 12.94
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1347'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1347', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3763588 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10361s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:24.664303019 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1730] 1 False 11.74
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1730'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1730', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3763757 parent=3536493 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050838730 Running inference - currFrameIdx > numFramesCalibration ********** 0.23020s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.23025s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.23027s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.23028s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.23033s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.23044s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.23052s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_715] 1 False 12.57
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_715'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_715', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-77' pid=3763808 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6781s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:26.252712216 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-77: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1310] 1 False 17.37
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1310'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1310', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3764024 parent=3536559 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8946s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:33.564286317 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1490] 1 False 19.50
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1490'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1490', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-73' pid=3764875 parent=3536280 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3188s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc(): corrupted top size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1595] 1 False 13.19
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1595'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1595', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3764876 parent=3536928 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8531s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1889] 1 False 16.08
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1889'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1889', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3765023 parent=3536277 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3444s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:37.786894014 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1268] 1 False 11.69
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1268'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1268', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3765261 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8144s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:34.666920797 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1239] 1 False 11.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1239'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1239', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-75' pid=3765487 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8805s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:34.685663498 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-75: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1615] 1 False 14.10
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1615'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1615', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-78' pid=3765919 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066723357 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): unaligned tcache chunk detected
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1270] 1 False 14.78
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1270'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1270', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3766162 parent=3536493 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5190s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5204s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:39.803371425 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1475] 1 False 17.18
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1475'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1475', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-80' pid=3766192 parent=3536285 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7506s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1069667847 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:42.015064794 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1894] 1 False 20.36
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1894'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1894', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3766257 parent=3536424 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9469s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9497s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:45.708677718 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1749] 1 False 20.96
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1749'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1749', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-81' pid=3766494 parent=3536274 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name
------------------------------Captured stderr call------------------------------
malloc_consolidate(): invalid chunk size
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_819] 1 False 15.90
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_819'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_819', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3766763 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9956s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:46.298680919 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1307] 1 False 19.65
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1307'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1307', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-76' pid=3766826 parent=3536271 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3681s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3695s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ========================
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:50.114702921 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] terminate called after throwing an instance of 'onnxruntime::OnnxRuntimeException' what(): /root/onnxruntime/onnxruntime/core/framework/bfc_arena.cc:92 onnxruntime::BFCArena::Chunk* onnxruntime::BFCArena::ChunkFromHandle(onnxruntime::BFCArena::ChunkHandle) h < chunks_.size() was false.
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1930] 1 False 10.06
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1930'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1930', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3766943 parent=3536730 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3584s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:41.780931756 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -7 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_861] 1 False 16.20
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_861'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_861', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3767126 parent=3536629 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9253s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:48.820566744 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1781] 1 False 13.03
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1781'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1781', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-83' pid=3767414 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8127s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8152s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:46.796621111 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-83: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1902] 1 False 15.97
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1902'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1902', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-76' pid=3767660 parent=3536460 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:50.673259643 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-76: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1195] 1 False 10.76
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1195'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1195', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3767661 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:45.543615817 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_810] 1 False 9.15
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_810'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_810', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3768154 parent=3536324 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3885s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:45.802253263 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1384] 1 False 17.07
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1384'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1384', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-76' pid=3768208 parent=3537059 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7709s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7732s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1050100735 Running inference - currFrameIdx > numFramesCalibration ********** 0.60183s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.60193s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.60199s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.60202s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.60206s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.60233s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.60247s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.107973s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.108105s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.108115s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24899309 bytes MEM: Free's : 25 free's of 24899309 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1439] 1 False 11.39
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1439'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1439', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -6
E assert -6 == 0
E + where -6 = <Process name='Process-79' pid=3768468 parent=3536962 stopped exitcode=-SIGABRT>.exitcode

test_tidl_unit.py:123: AssertionError[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1062831271 Running inference - currFrameIdx > numFramesCalibration **********
------------------------------Captured stderr call------------------------------
malloc(): invalid size (unsorted)
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_902] 1 False 13.13
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_902'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_902', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-78' pid=3768599 parent=3536289 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.434s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5502s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:52.386632652 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1] Process Process-78: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -6 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1471] 1 False 13.63
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1471'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1471', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-81' pid=3769086 parent=3536730 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7290s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7309s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name ********** Frame Index 1066044866 Running inference - currFrameIdx > numFramesCalibration ********** 0.114690s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.114700s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.114703s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.114707s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.114710s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.114729s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.114737s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1721] 1 False 15.69
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1721'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1721', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3769183 parent=3536285 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4404s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4411s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:58.176159519 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1787] 1 False 15.69
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1787'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1787', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3769184 parent=3536831 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5972s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:58.177515190 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 2 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_877] 1 False 11.03
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_877'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_877', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-82' pid=3769313 parent=3536265 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:53.972495621 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1] Process Process-82: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -5 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_911] 1 False 13.32
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_911'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_911', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-80' pid=3769342 parent=3536562 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.235s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2555s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:56.597103891 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0] Process Process-80: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 6 is not in valid range [-1,0]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1159] 1 False 9.90
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1159'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1159', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-83' pid=3769849 parent=3536268 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7659s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:55.478392206 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1] Process Process-83: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis -4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_839] 1 False 10.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_839'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_839', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-79' pid=3770030 parent=3536359 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5511s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5522s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:56.597104018 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1] Process Process-79: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 3 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1025] 1 False 12.54
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1025'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1025', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-84' pid=3770141 parent=3536765 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1292s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1295s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:59.524663326 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis Process Process-84: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.InvalidArgument: [ONNXRuntimeError] : 2 : INVALID_ARGUMENT : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: 'axes' has a duplicate axis
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_789] 1 False 10.09
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_789'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_789', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: 1
E assert 1 == 0
E + where 1 = <Process name='Process-81' pid=3770427 parent=3536928 stopped exitcode=1>.exitcode

test_tidl_unit.py:123: AssertionError[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3080s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
------------------------------Captured stderr call------------------------------
2025-05-07 04:15:58.774969349 [E:onnxruntime:, sequential_executor.cc:514 ExecuteKernel] Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1] Process Process-81: Traceback (most recent call last): File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 314, in _bootstrap self.run() File "/home/tidl/.pyenv/versions/3.10.16/lib/python3.10/multiprocessing/process.py", line 108, in run self._target(*self._args, **self._kwargs) File "/home/tidl/pranav/edgeai-benchmark/tests/tidl_unit/test_tidl_unit.py", line 206, in perform_tidl_unit_oneprocess results_list = onnxruntime_wrapper.run_import(tidl_unit_dataset[0]) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 58, in run_import output = self._run(input_data, output_keys) File "/home/tidl/pranav/edgeai-benchmark/edgeai_benchmark/core/onnxrt_runtime.py", line 91, in _run outputs = self.interpreter.run(output_keys, input_data) File "/home/tidl/.pyenv/versions/benchmark/lib/python3.10/site-packages/onnxruntime/capi/onnxruntime_inference_collection.py", line 217, in run return self._sess.run(output_names, input_feed, run_options) onnxruntime.capi.onnxruntime_pybind11_state.RuntimeException: [ONNXRuntimeError] : 6 : RUNTIME_EXCEPTION : Non-zero status code returned while running Unsqueeze node. Name:'' Status Message: /root/onnxruntime/onnxruntime/core/providers/common.h:23 int64_t onnxruntime::HandleNegativeAxis(int64_t, int64_t) axis >= -tensor_rank && axis <= tensor_rank - 1 was false. axis 4 is not in valid range [-2,1]
Failed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1342] 1 False 8.69
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3

no_subprocess = False, tidl_offload = True, run_infer = False, operator_tests_root_fixture = 'tidl_unit_test_data/operator/'
test_name = 'Unsqueeze_1342'

@pytest.mark.parametrize(("test_name"), operator_tests_to_run)
def test_tidl_unit_operator(no_subprocess : bool, tidl_offload : bool, run_infer : bool, operator_tests_root_fixture : str, test_name : str):
'''
Pytest for tidl unit operator tests using the edgeai-benchmark framework
'''
testdir_parent = operator_tests_root_fixture
for i in range(len(operator_tests_to_run)):
if operator_tests_to_run[i] == test_name:
testdir_parent = operator_tests_parent_dir[i]
break

> perform_tidl_unit(no_subprocess=no_subprocess,
tidl_offload = tidl_offload,
run_infer = run_infer,
test_name = test_name,
test_suite = "operator",
testdir_parent = testdir_parent)

test_tidl_unit.py:70:
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
test_tidl_unit.py:89: in perform_tidl_unit
perform_tidl_unit_subprocess(tidl_offload = tidl_offload,
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tidl_offload = True, run_infer = False, test_name = 'Unsqueeze_1342', test_suite = 'operator'
testdir_parent = 'tidl_unit_test_data/operator/Unsqueeze'

def perform_tidl_unit_subprocess(tidl_offload : bool, run_infer : bool, test_name : str, test_suite : str, testdir_parent : str):
'''
Perform an tidl unit test using a subprocess (in order to properly capture output for fatal errors)
Called by perform_tidl_unit
'''

kwargs = {"tidl_offload" : tidl_offload,
"run_infer" : run_infer,
"test_name" : test_name,
"test_suite" : test_suite,
"testdir_parent" : testdir_parent}

p = Process(target=perform_tidl_unit_oneprocess, kwargs=kwargs)
p.start()


# Note: This timeout parameter must be lower than the pytest-timeout parameter
# passed to the pytest command (on the command line or in pytest.ini)
p.join(timeout=600)
if p.is_alive():
p.terminate()

# Cleanup leftover files
for f in glob.glob("/dev/shm/vashm_buff_*"):
os.remove(f)

> assert p.exitcode == 0, f"Received nonzero exit code: {p.exitcode}"
E AssertionError: Received nonzero exit code: -11
E assert -11 == 0
E + where -11 = <Process name='Process-77' pid=3770799 parent=3536460 stopped exitcode=-SIGSEGV>.exitcode

test_tidl_unit.py:123: AssertionError[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.89s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== 0.266729s: VX_ZONE_ERROR: [ownObjectDeInit:171] Is graph use failed, index: 0 0.266735s: VX_ZONE_ERROR: [ownObjectDeInit:177] Is node use failed, index: 0 0.266736s: VX_ZONE_ERROR: [ownObjectDeInit:183] Is kernel use failed, index: 0 0.266737s: VX_ZONE_ERROR: [ownObjectDeInit:184] kernel name: org.khronos.openvx.absdiff 0.266739s: VX_ZONE_ERROR: [ownObjectDeInit:196] Is user data object use failed, index: 0 0.266743s: VX_ZONE_ERROR: [ownObjectDeInit:240] Is tensor use failed, index: 0 0.266745s: VX_ZONE_ERROR: [ownObjectDeInit:282] Is error use failed, index: 0 0.310311s: VX_ZONE_ERROR: [ownPosixObjectDeInit:300] Deiniting event at index: 0 failed 0.310321s: VX_ZONE_ERROR: [ownPosixObjectDeInit:311] Deiniting queue at index: 41 failed 0.310323s: VX_ZONE_ERROR: [ownPosixObjectDeInit:333] Deiniting mutex at index: 10 failed MEM: Deinit ... !!! MEM: Alloc's: 25 alloc's of 24026861 bytes MEM: Free's : 25 free's of 24026861 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_682] 1 True 18.93
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3592s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_307] 1 True 23.93
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7874s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_394] 1 True 21.83
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.215s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3697s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_549] 1 True 23.98
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.421s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7257s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_78] 1 True 10.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_594] 1 True 17.55
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6886s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6909s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_495] 1 True 10.38
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10077s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_235] 1 True 15.22
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4590s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1824] 1 False 20.84
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3998s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_303] 1 True 20.57
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.200s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2934s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_210] 1 True 10.19
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.287s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2745s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2757s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_675] 1 False 19.84
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.605s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_38] 1 True 23.25
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.568s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10980s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11004s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1875] 1 False 13.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4720s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4741s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_26] 1 True 11.44
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4227s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_215] 1 True 10.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4897s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_263] 1 True 16.76
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9123s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1298] 1 False 22.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9803s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1827] 1 False 15.63
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1091] 1 False 15.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.284s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_266] 1 True 14.50
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_254] 1 True 11.90
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_915] 1 False 13.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9209s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_847] 1 True 19.91
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9052s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_565] 1 True 15.27
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5174s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_181] 1 True 12.98
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8377s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8393s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_406] 1 True 16.63
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_180] 1 True 12.22
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5892s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_302] 1 True 18.51
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_345] 1 True 23.71
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_241] 1 True 13.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10360s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10392s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_102] 1 True 19.49
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2910s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_291] 1 True 17.80
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3757s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3773s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_56] 1 True 10.30
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4319s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1235] 1 False 21.00
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7938s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_14] 1 True 11.55
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6107s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_79] 1 True 12.57
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.606s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7052s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_568] 1 True 18.85
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_336] 1 True 16.93
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.229s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_591] 1 True 19.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6650s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6668s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1211] 1 False 15.59
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_274] 1 True 20.82
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_104] 1 True 17.57
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8175s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_508] 1 True 10.94
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4563s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_445] 1 True 24.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_481] 1 True 11.07
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8885s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8920s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_584] 1 True 16.05
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5207s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_158] 1 True 14.28
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4929s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_368] 1 True 14.54
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3316s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_51] 1 True 14.58
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4322s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4336s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_277] 1 True 17.05
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6718s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6735s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_23] 1 True 22.32
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3541s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_388] 1 True 10.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.388s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_610] 1 True 16.84
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9357s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1147] 1 False 22.43
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3086s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3101s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_2] 1 True 17.37
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1057] 1 False 14.72
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5166s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_203] 1 True 22.03
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.526s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9837s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9866s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_106] 1 True 14.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9359s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_437] 1 True 22.53
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_108] 1 True 16.92
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4801s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1258] 1 False 14.70
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3732s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_599] 1 True 15.24
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.416s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4653s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_117] 1 True 10.85
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3793s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_405] 1 True 9.79
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6345s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_595] 1 True 23.95
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7983s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8007s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_149] 1 True 13.76
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8041s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_74] 1 True 10.27
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_296] 1 True 13.23
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5454s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5473s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_457] 1 True 16.51
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4039s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_177] 1 True 14.09
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.62s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.65s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.585s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9108s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_131] 1 True 12.79
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5051s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_598] 1 True 18.46
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.52s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.54s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.583s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9474s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_271] 1 True 13.87
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_390] 1 True 18.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.556s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9850s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9881s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_361] 1 True 16.18
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.48s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9520s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_265] 1 True 18.61
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3738s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3753s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_111] 1 True 16.76
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9375s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9402s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_310] 1 True 20.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.525s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8887s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8916s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_172] 1 True 18.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_821] 1 True 13.51
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.420s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1086] 1 False 9.39
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8299s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8318s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_381] 1 True 23.57
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.35s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.432s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.12454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.12520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.12630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.12681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.12784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.12837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.12902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.12955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.13019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.13083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.13163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.13232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.13310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.13369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.13441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.13517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.13640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.13700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.13760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.13851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.13908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.13989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.14126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.14226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.14282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.14385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.14552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.14676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.14756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.14853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.14984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.14991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15015s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1198] 1 False 15.70
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5664s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5675s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_320] 1 True 9.42
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1023] 1 False 9.61
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.836s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.2787s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6714s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6727s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_67] 1 True 11.59
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8887s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_43] 1 True 14.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.564s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8865s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_346] 1 True 9.38
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6825s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6844s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_70] 1 True 9.98
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_186] 1 True 18.98
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_577] 1 True 22.18
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9018s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9046s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_44] 1 True 19.12
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8759s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_483] 1 True 14.20
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9945s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_573] 1 True 14.09
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10237s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1056] 1 False 20.24
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8991s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_300] 1 True 9.98
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.454s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_667] 1 True 17.14
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.608s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12488s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12517s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_338] 1 True 19.85
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4223s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_348] 1 True 16.15
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.14328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.14429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.14504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.15034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.15081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.15186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.15239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.15762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.15868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.15945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.16012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.16120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.16184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.16238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.16353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.16410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.16488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.16583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.16648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.16652s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.16670s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_306] 1 True 10.36
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.565s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_475] 1 True 10.53
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3755s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3769s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_222] 1 True 18.17
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8528s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8548s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_757] 1 True 14.14
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9124s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_6] 1 True 17.60
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_607] 1 True 15.09
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_105] 1 True 9.78
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8266s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1805] 1 False 19.64
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7780s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7818s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_383] 1 True 23.63
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9088s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9113s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_787] 1 True 15.71
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8673s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8701s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_97] 1 True 14.27
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7762s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_12] 1 True 11.51
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3732s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_883] 1 False 9.52
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.43s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.46s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.595s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_612] 1 True 14.02
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7582s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7602s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_421] 1 True 16.02
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_597] 1 True 16.70
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_36] 1 True 18.24
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4145s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_469] 1 True 16.97
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.638s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10462s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_471] 1 True 21.41
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3429s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_535] 1 True 16.86
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3778s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_554] 1 True 9.16
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3597s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_523] 1 True 21.65
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8662s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_744] 1 True 12.71
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9139s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 28007533 bytes MEM: Free's : 26 free's of 28007533 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_283] 1 True 18.25
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9023s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_620] 1 True 19.87
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4074s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4092s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_298] 1 True 19.53
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2112s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_82] 1 True 11.36
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3559s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3570s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_611] 1 True 15.81
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4453s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_139] 1 True 11.75
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.407s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5821s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5841s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_556] 1 True 13.01
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_545] 1 True 11.98
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6546s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6565s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_387] 1 True 10.58
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.335s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4479s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_768] 1 True 14.60
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.378s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4534s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_373] 1 True 15.58
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4794s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4804s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_127] 1 True 17.56
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8891s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_40] 1 True 13.68
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7412s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_193] 1 True 10.61
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6213s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_137] 1 True 12.78
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_76] 1 True 13.38
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3366s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_410] 1 True 11.97
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10164s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_449] 1 True 17.52
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_206] 1 True 11.89
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.513s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8769s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8794s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_786] 1 True 10.34
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8330s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8352s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_98] 1 True 18.77
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3387s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_163] 1 True 11.34
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.461s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7130s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_24] 1 True 14.65
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3500s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1820] 1 False 10.10
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_58] 1 True 9.93
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7111s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7131s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_112] 1 True 20.33
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_197] 1 True 14.52
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.349s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4321s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4337s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_478] 1 True 16.64
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3845s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_572] 1 True 10.28
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_392] 1 True 19.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6320s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6332s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_697] 1 True 18.04
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.563s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10459s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_528] 1 True 14.02
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7160s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_10] 1 True 16.56
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3576s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_225] 1 True 16.52
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3936s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3951s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_596] 1 True 18.68
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9315s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_631] 1 True 17.85
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.437s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8990s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_407] 1 True 11.77
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5009s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_324] 1 True 16.35
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3398s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_270] 1 True 14.44
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.271s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4117s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4129s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_622] 1 True 13.44
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5943s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_621] 1 True 13.44
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.40s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4614s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_281] 1 True 16.86
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8424s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8444s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_143] 1 True 15.31
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_42] 1 True 15.44
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2667s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2677s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_397] 1 True 15.42
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3930s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_230] 1 True 13.99
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4094s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_308] 1 True 19.77
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9344s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9377s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_529] 1 True 15.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_427] 1 True 10.64
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5544s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_615] 1 True 10.54
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4591s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_452] 1 True 11.45
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3634s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_4] 1 True 14.41
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4207s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4221s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_5] 1 True 22.69
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8881s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8905s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_187] 1 True 17.98
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_333] 1 True 16.14
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3250s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3260s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_244] 1 True 19.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.242s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2400s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_374] 1 True 10.24
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_614] 1 True 14.16
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3206s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3218s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_96] 1 True 12.40
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3632s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_415] 1 True 18.93
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5924s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5941s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_184] 1 True 16.10
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7469s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_208] 1 True 18.70
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6450s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6491s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_507] 1 True 14.03
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3185s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_364] 1 True 10.52
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6599s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6623s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_7] 1 True 20.73
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671785 bytes MEM: Free's : 26 free's of 18671785 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_20] 1 True 18.02
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5640s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_350] 1 True 16.26
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4644s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_213] 1 True 9.55
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3601s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3611s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_192] 1 True 21.99
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6176s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_815] 1 False 9.08
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_35] 1 True 22.55
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9536s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_305] 1 True 17.23
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.597s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9487s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9512s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_420] 1 True 10.54
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_325] 1 True 15.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.577s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10126s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_304] 1 True 16.57
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.711s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8915s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8945s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_379] 1 True 17.07
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_318] 1 True 15.58
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8731s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_288] 1 True 13.74
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3639s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_182] 1 True 13.70
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.104s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.106s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9569s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9601s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_261] 1 True 10.69
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7847s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_466] 1 True 14.51
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6273s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6289s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_444] 1 True 22.60
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9705s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9739s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_161] 1 True 11.85
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8941s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_590] 1 True 14.60
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.256s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3937s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_243] 1 True 21.96
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7831s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7858s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_289] 1 True 15.92
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3849s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3860s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_356] 1 True 15.83
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4547s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4561s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_152] 1 True 19.59
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3544s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_224] 1 True 9.47
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5403s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_179] 1 True 13.93
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.496s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6499s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6530s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_501] 1 True 17.59
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3838s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3850s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_162] 1 True 9.35
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7276s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_34] 1 True 11.56
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8040s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8069s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_341] 1 True 21.59
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8691s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8712s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_680] 1 True 18.75
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.572s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7653s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_493] 1 True 20.84
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_539] 1 True 9.91
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3114s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_490] 1 True 20.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8333s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_349] 1 True 16.73
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8173s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_49] 1 True 17.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4368s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_246] 1 True 10.30
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.6s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2708s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1006] 1 False 11.25
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.487s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7960s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_273] 1 True 12.06
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4446s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_399] 1 True 23.46
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7911s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_103] 1 True 14.63
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.610s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9942s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_423] 1 True 22.27
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6352s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_219] 1 True 14.67
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4031s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4044s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1184] 1 False 14.70
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.538s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10079s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10103s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_360] 1 True 12.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_422] 1 True 10.25
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.228s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_211] 1 True 16.07
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4256s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4273s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_712] 1 True 11.51
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4853s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4877s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1241] 1 False 15.72
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4468s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_292] 1 True 18.87
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7635s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_533] 1 True 9.84
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_677] 1 True 17.90
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2669s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2679s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1119] 1 False 11.26
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8750s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_604] 1 True 21.48
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3369s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3384s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1881] 1 False 12.27
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8292s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_352] 1 True 21.13
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7878s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7912s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_285] 1 True 10.78
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.471s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9958s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_484] 1 True 14.78
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.509s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8785s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8811s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_402] 1 True 21.13
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_678] 1 False 20.78
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6011s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6027s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_840] 1 True 13.33
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.343s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1215] 1 False 14.32
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.413s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4616s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_509] 1 True 19.09
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7859s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_467] 1 True 13.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9105s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_301] 1 True 17.87
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3311s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_624] 1 True 18.54
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1125] 1 False 15.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6346s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6370s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_13] 1 True 15.82
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5181s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5202s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_196] 1 True 21.91
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9253s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_419] 1 True 14.59
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4670s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_61] 1 True 19.95
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10744s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10766s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_176] 1 True 19.72
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9155s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9179s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_515] 1 True 23.53
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.580s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9041s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9065s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_455] 1 True 10.11
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.544s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6750s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_645] 1 True 16.78
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3548s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_561] 1 True 12.41
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.470s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8431s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_344] 1 True 12.64
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8577s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8607s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_205] 1 True 14.33
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3368s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_154] 1 True 16.52
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4710s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4720s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_204] 1 True 21.50
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_322] 1 True 9.95
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3747s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3761s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_218] 1 True 16.79
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5596s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5612s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_827] 1 True 14.77
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_751] 1 True 16.34
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9537s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9568s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_448] 1 True 10.51
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4382s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_418] 1 True 17.99
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3612s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_799] 1 True 23.57
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4250s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1070] 1 False 14.18
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10962s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_516] 1 True 11.40
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7311s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7339s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_626] 1 True 11.10
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.47s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.49s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.629s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5908s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_299] 1 True 12.95
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9533s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9560s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_73] 1 True 13.15
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.688s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10237s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_519] 1 True 12.78
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.324s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3992s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_814] 1 True 14.61
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.80s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.81s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.419s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4132s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4150s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_284] 1 True 9.79
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_527] 1 True 13.91
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.408s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5267s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_87] 1 True 21.61
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9226s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_542] 1 True 20.69
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.577s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10247s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1689] 1 False 12.16
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5762s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5779s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_37] 1 True 17.42
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8880s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8912s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_99] 1 True 10.00
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_83] 1 True 14.28
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2921s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2933s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_506] 1 True 13.10
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8562s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_429] 1 True 9.85
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3551s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3564s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_312] 1 True 13.86
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5313s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_569] 1 True 23.17
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.293s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3264s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3278s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_505] 1 True 22.62
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.355s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3863s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3878s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_9] 1 True 16.22
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.246s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2515s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_473] 1 True 12.52
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4145s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_480] 1 True 13.53
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8532s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8552s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1079] 1 False 20.83
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.366s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6004s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6025s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_259] 1 True 9.28
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5053s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_520] 1 True 17.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9312s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9344s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_602] 1 True 17.47
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7020s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7047s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_521] 1 True 18.83
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3359s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_552] 1 True 16.88
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8778s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8799s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_279] 1 True 11.63
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3057s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3073s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_382] 1 True 20.34
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.334s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3578s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3595s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1053] 1 False 14.70
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6976s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7003s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_459] 1 True 20.43
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5290s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_29] 1 True 16.97
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9068s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_128] 1 True 15.44
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7364s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_403] 1 True 18.07
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8934s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8959s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1221] 1 False 10.70
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.481s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6054s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6081s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_433] 1 True 10.31
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.260s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4016s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4032s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_124] 1 True 18.08
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.564s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9827s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_886] 1 False 11.04
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3967s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3979s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_857] 1 True 19.23
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_653] 1 False 20.16
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.564s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9363s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_511] 1 True 9.33
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.283s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2767s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2781s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_125] 1 True 15.00
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8828s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8855s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_644] 1 True 20.42
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10096s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_745] 1 True 13.84
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.345s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4080s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4108s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1083] 1 False 19.45
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.431s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_201] 1 True 9.54
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_80] 1 True 18.92
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8869s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_120] 1 True 15.38
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.913s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9600s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1650] 1 False 15.75
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.530s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9383s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_763] 1 True 13.14
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2944s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2961s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_575] 1 True 11.11
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_216] 1 True 14.82
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.553s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9928s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9965s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1102] 1 False 15.14
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8384s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1012] 1 False 20.65
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3807s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_453] 1 True 16.76
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4048s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4060s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_309] 1 True 13.91
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8524s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_428] 1 True 20.00
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9454s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_57] 1 True 12.63
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8583s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_228] 1 True 10.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.265s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4425s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_896] 1 False 20.73
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7275s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7300s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_267] 1 True 10.72
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_836] 1 True 10.01
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.212s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3226s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_489] 1 True 14.02
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7483s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_579] 1 True 14.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.476s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7239s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_17] 1 True 18.41
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6172s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_195] 1 True 11.93
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.243s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3418s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_253] 1 True 10.98
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2573s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2585s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_141] 1 True 21.20
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8961s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8985s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_398] 1 True 19.11
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.370s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6331s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_413] 1 True 11.45
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.336s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3636s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3651s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_233] 1 True 9.22
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_367] 1 True 9.49
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.507s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9205s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9230s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_68] 1 True 18.43
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4192s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4212s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_447] 1 True 16.18
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.610s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6988s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_343] 1 True 19.60
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8687s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_746] 1 True 13.07
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3931s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3946s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1143] 1 False 10.25
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.4576s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.12312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.12454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.12531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.12610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.12694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.12797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.12873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.12942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.13236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.13340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.17803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.18181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.18314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.18385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.18462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.18547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.18639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.18740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.18828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.18900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.18983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.19085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.19192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.19265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.19333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.20028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20575s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20615s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_371] 1 True 22.37
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.308s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3918s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_377] 1 True 12.50
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7445s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_668] 1 True 21.22
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.344s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6029s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1864] 1 False 12.71
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3447s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_136] 1 True 14.82
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_151] 1 True 12.38
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4183s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4198s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1029] 1 False 9.10
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.363s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3232s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3245s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_362] 1 True 18.66
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_242] 1 True 20.11
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9874s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_334] 1 True 18.70
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.572s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8261s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8293s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_465] 1 True 12.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3911s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3927s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_791] 1 True 12.51
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4324s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1153] 1 False 23.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3340s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_502] 1 True 13.17
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4414s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4427s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_342] 1 True 13.68
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.550s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8380s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_593] 1 True 24.37
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8390s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_347] 1 True 23.66
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.591s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10468s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10498s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_133] 1 True 16.72
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3765s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3776s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_558] 1 True 15.96
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.610s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12150s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_494] 1 True 12.04
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3803s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3819s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1129] 1 False 15.70
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.390s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3728s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_286] 1 True 11.25
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3354s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3363s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_856] 1 False 19.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.516s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7760s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7775s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_625] 1 True 16.31
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6993s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7021s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_585] 1 True 23.12
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5977s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_71] 1 True 23.21
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8335s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8353s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_643] 1 False 14.04
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11374s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11426s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1044] 1 False 17.47
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.534s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8898s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_830] 1 True 12.49
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.765s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18701437 bytes MEM: Free's : 26 free's of 18701437 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_19] 1 True 12.56
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.566s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.8267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.8344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.9019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.9191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.14637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.15114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.15208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.15274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.15351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.15423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.15427s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.15457s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_662] 1 True 19.25
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.288s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5247s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_482] 1 True 18.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9070s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_209] 1 True 19.17
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8580s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_69] 1 True 12.03
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3777s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3792s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_635] 1 False 9.43
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3663s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_363] 1 True 11.12
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.554s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8422s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8446s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_790] 1 True 13.38
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.273s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3775s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3789s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_237] 1 True 17.15
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6948s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6973s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1282] 1 False 15.05
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3965s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3982s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_340] 1 True 17.36
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10514s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_517] 1 True 13.60
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_551] 1 True 19.37
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10656s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10681s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_92] 1 True 12.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6857s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_400] 1 True 18.38
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4071s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_48] 1 True 13.00
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3467s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3484s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_540] 1 True 11.94
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_332] 1 True 13.67
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_436] 1 True 17.50
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.281s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2787s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_231] 1 True 18.47
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7114s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_619] 1 True 16.62
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_115] 1 True 19.11
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4442s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_408] 1 True 14.41
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9631s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9656s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_603] 1 True 24.37
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8038s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_908] 1 False 10.41
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_77] 1 True 20.11
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.384s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8050s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_52] 1 True 12.40
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.508s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6168s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6192s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_121] 1 True 17.90
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3320s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_499] 1 True 15.38
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8216s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8246s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_544] 1 True 16.95
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_450] 1 True 14.12
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3167s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3181s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_898] 1 False 14.84
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3156s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_168] 1 True 17.18
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4174s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4194s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_240] 1 True 12.79
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.444s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7171s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_315] 1 True 10.93
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.247s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3432s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3439s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_256] 1 True 13.62
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_223] 1 True 17.09
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.368s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4188s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_486] 1 True 19.32
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5177s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5203s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_488] 1 True 20.07
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4104s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4119s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_313] 1 True 19.10
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.387s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3285s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3299s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_86] 1 True 8.89
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.485s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7694s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_41] 1 True 16.01
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3064s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3077s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_25] 1 True 21.93
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.267s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3514s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_588] 1 True 16.32
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.196s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4405s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_155] 1 True 20.19
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8740s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8771s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_175] 1 True 9.64
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_443] 1 True 20.47
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6703s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6726s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 58038661 bytes MEM: Free's : 26 free's of 58038661 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_328] 1 True 14.07
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.448s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5461s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_803] 1 True 15.95
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4013s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4031s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_417] 1 True 14.06
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.305s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3506s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_474] 1 True 17.24
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.458s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8953s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8978s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_220] 1 True 19.96
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3413s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3428s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1923] 1 False 18.55
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10889s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10928s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_28] 1 True 11.45
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4129s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4148s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1852] 1 False 16.88
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.472s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8233s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18681997 bytes MEM: Free's : 26 free's of 18681997 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1152] 1 False 12.44
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3796s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3813s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_351] 1 True 10.94
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3752s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_335] 1 True 12.32
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.323s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3075s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3087s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_214] 1 True 15.20
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.581s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10027s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10057s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_321] 1 True 17.07
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.43s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.586s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9135s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9167s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_39] 1 True 19.26
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.299s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3605s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3619s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_496] 1 True 15.77
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.515s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9871s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9895s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1001] 1 False 12.32
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.404s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.12727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.13164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.13312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.13383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.13484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.13538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.13641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.13693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.13785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.13850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.13891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.13977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.14035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.14200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.14288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.14372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.14428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.14514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.14586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.14637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.14746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.14846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.14928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.15030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.15106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.15181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.15279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.15342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.15402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.19239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.19615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.19682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.19746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.19812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.19866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.19997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.20064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.20123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.20195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.20266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.20320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.20324s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.20357s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_430] 1 True 16.99
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7062s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7076s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_559] 1 True 16.98
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9607s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9636s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_538] 1 True 13.18
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.303s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3642s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3657s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_30] 1 True 23.21
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9536s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_497] 1 True 20.70
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1035s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8463s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_385] 1 True 15.14
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7521s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7542s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_339] 1 True 11.34
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_81] 1 True 15.30
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.500s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_532] 1 True 14.79
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4012s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4024s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_32] 1 True 9.36
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9238s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_287] 1 True 13.00
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3629s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3644s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_546] 1 True 17.82
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6624s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_278] 1 True 18.01
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3657s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3672s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_567] 1 True 14.08
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7392s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7412s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_355] 1 True 14.88
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_11] 1 True 15.33
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8436s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8463s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_199] 1 True 10.17
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.389s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6314s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_801] 1 True 20.95
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18721421 bytes MEM: Free's : 26 free's of 18721421 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_378] 1 True 12.14
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.600s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10722s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10753s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_138] 1 True 15.25
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8643s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8667s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_247] 1 True 10.38
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_337] 1 True 14.92
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.459s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_178] 1 True 20.80
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.512s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8658s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_660] 1 False 15.31
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4448s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_816] 1 False 12.30
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2836s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_282] 1 True 13.63
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_118] 1 True 17.65
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.361s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5530s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_22] 1 True 17.59
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8296s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_170] 1 True 12.88
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.415s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5452s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_395] 1 True 17.86
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4451s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4472s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_431] 1 True 23.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8391s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8414s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_438] 1 True 16.28
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.578s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9692s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9719s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_101] 1 True 12.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5098s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5117s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_64] 1 True 16.45
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8806s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8831s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_60] 1 True 21.16
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4979s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4997s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_257] 1 True 13.76
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.90s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.93s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.678s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9374s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_258] 1 True 13.16
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9326s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_190] 1 True 9.89
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7059s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_330] 1 True 16.49
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3410s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3423s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_412] 1 True 9.87
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3994s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4010s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_50] 1 True 21.99
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.309s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_252] 1 True 16.98
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.339s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3449s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3466s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_530] 1 True 9.44
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3723s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3736s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_269] 1 True 20.74
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6210s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6232s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_94] 1 True 14.11
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10382s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10419s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_582] 1 True 20.56
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4538s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_329] 1 True 9.18
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.369s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5137s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5154s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_311] 1 True 16.83
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.441s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7608s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7632s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_359] 1 True 18.13
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6575s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_27] 1 True 15.35
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.249s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3950s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3968s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_156] 1 True 19.49
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3317s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1178] 1 False 12.45
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3736s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3748s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_226] 1 True 18.20
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4262s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4282s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_47] 1 True 22.89
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.486s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5814s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_434] 1 True 21.53
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.537s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7420s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_536] 1 True 12.38
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4717s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_319] 1 True 21.36
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8641s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_442] 1 True 9.91
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4632s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4649s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_934] 1 False 20.63
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.455s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7865s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_194] 1 True 17.92
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.272s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3581s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3599s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_623] 1 True 9.67
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1026s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_146] 1 True 18.53
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10818s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10852s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_331] 1 True 11.33
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10036s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10063s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_89] 1 True 23.34
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7715s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_414] 1 True 10.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4196s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_525] 1 True 9.72
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8568s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_541] 1 True 21.70
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8685s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8713s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_460] 1 True 13.77
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4671s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_375] 1 True 17.70
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.518s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8968s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8995s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_727] 1 True 20.85
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8019s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_249] 1 True 18.41
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9351s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_589] 1 True 18.52
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.480s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11783s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11811s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_479] 1 True 16.54
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.443s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3385s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3398s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_659] 1 True 14.29
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.341s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4452s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_255] 1 True 11.55
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.285s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3771s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3787s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_262] 1 True 19.35
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.560s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9271s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9301s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_245] 1 True 23.17
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.321s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3907s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_113] 1 True 16.20
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.291s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4196s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1683] 1 False 18.27
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.306s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3662s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_294] 1 True 10.47
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.310s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6077s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6095s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_59] 1 True 12.92
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.270s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2579s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_297] 1 True 20.65
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.379s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4162s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_463] 1 True 17.76
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7652s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_491] 1 True 9.69
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6851s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6876s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_580] 1 True 12.65
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7525s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_132] 1 True 11.80
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.401s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7387s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_464] 1 True 16.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3510s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1637] 1 False 11.58
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.374s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19629037 bytes MEM: Free's : 26 free's of 19629037 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_357] 1 True 14.81
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4072s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4085s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_411] 1 True 14.15
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.322s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3246s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3262s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_592] 1 True 24.08
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9300s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9330s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_140] 1 True 10.46
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.542s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10370s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10397s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_560] 1 True 16.47
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4173s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4190s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_409] 1 True 9.48
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.316s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4318s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4334s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_93] 1 True 13.70
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.571s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10093s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10123s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_323] 1 True 9.75
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6455s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6471s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24027245 bytes MEM: Free's : 26 free's of 24027245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_232] 1 True 20.13
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.333s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3817s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3832s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_454] 1 True 21.57
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.495s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9527s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_571] 1 True 21.65
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.249s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.256s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.815s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10093s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10125s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_126] 1 True 11.00
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.48s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.50s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.601s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8428s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8448s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_91] 1 True 20.57
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.340s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4611s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4631s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1794] 1 False 10.25
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9683s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9716s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_221] 1 True 17.71
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.505s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9347s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9376s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_174] 1 True 14.74
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.314s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3417s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_425] 1 True 10.11
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4106s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_370] 1 True 14.55
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7724s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7749s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_239] 1 True 18.52
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.523s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8767s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8797s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_88] 1 True 16.76
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.41s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.42s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.667s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11464s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11499s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_581] 1 True 12.02
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.372s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4323s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_537] 1 True 16.14
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.453s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6281s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6305s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1895] 1 False 20.68
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6984s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7005s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_606] 1 True 19.54
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.352s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3512s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_55] 1 True 13.88
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5947s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_227] 1 True 10.16
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6801s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6829s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_485] 1 True 14.79
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.514s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8355s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8379s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_627] 1 True 10.44
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.504s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_66] 1 True 14.00
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10493s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_144] 1 True 21.20
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.418s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7329s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_250] 1 True 21.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8034s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8058s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_272] 1 True 10.06
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4743s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4758s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_116] 1 True 15.74
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.482s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7844s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7873s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_435] 1 True 15.23
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2836s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_166] 1 True 11.68
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3350s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3360s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1160] 1 False 10.67
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.462s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9158s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_316] 1 True 18.65
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8529s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_217] 1 True 21.31
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.636s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.7679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.10397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.11449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.11522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.12235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.12242s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.12271s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_570] 1 True 16.34
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.338s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4109s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_608] 1 True 20.62
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8421s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_500] 1 True 15.05
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4169s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4183s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1128] 1 False 13.68
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.282s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5395s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5408s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_384] 1 True 17.36
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.546s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9151s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9177s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1066] 1 False 11.29
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8241s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_135] 1 True 11.47
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.466s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6734s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6763s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_236] 1 True 14.23
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10224s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10256s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1264] 1 False 11.57
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.469s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9030s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9052s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_440] 1 True 16.67
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.33s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9440s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9464s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1892] 1 False 14.48
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3373s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3385s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_446] 1 True 11.52
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3431s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_159] 1 True 15.69
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.371s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4341s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_33] 1 True 14.60
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.311s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3756s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_563] 1 True 10.23
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.399s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7138s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7158s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_142] 1 True 20.96
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.423s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7211s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7252s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_8] 1 True 17.15
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.664s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.7287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.7502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.7780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.8119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.8337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.8618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.9269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.10052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.10750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.10991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.11152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.11300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.11441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.11577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.11718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.11861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.12023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.12218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.12353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.12503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.12678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.12777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.12923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.13102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.13116s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.13151s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_185] 1 True 14.45
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.474s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5396s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1783] 1 False 15.49
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8294s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8327s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_583] 1 True 11.06
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.430s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7379s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7399s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1104] 1 False 13.15
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.304s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3795s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1933] 1 False 17.29
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.539s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.6024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.6279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.9016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.9155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.10144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.10241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.10340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.11071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.11228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.11334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.11418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.11579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.11724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.11737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.11767s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1786] 1 False 9.58
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.570s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5830s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9394s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9416s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_275] 1 True 10.18
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4637s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1243] 1 False 18.93
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.442s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6633s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6648s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_191] 1 True 10.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.506s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7625s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7671s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_123] 1 True 11.66
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.531s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8990s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9018s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_90] 1 True 15.04
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.501s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10334s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10362s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_518] 1 True 9.94
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.337s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4228s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4241s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_553] 1 True 14.81
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.497s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9996s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_164] 1 True 12.32
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.318s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3275s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_157] 1 True 19.97
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.295s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3148s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3155s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_130] 1 True 12.21
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9229s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9266s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_609] 1 True 12.97
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.34s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8441s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8481s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_276] 1 True 12.29
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5550s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5571s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_424] 1 True 13.26
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.491s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7309s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7328s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_404] 1 True 11.96
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8862s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8893s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_31] 1 True 13.14
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.632s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4417s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4433s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671785 bytes MEM: Free's : 26 free's of 18671785 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_376] 1 True 14.44
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.549s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5152s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9092s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9128s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_770] 1 True 11.00
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.502s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9808s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9828s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_458] 1 True 22.84
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5220s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5228s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_534] 1 True 13.62
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3231s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3244s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_574] 1 True 18.91
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.302s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4933s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4950s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_268] 1 True 10.83
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.362s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3952s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3971s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_456] 1 True 15.19
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.436s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8790s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8814s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_477] 1 True 13.71
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.463s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8869s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8897s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_633] 1 True 17.64
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.439s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6565s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_119] 1 True 12.35
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.380s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6443s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6461s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_564] 1 True 12.83
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.552s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5761s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8647s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8876s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8903s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_314] 1 True 19.61
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.611s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9010s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9037s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_167] 1 True 18.10
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.438s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8627s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8659s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_401] 1 True 16.60
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.357s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4193s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4210s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_150] 1 True 11.91
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.548s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8332s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8361s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_183] 1 True 23.74
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7822s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7848s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_326] 1 True 10.39
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.241s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2401s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2409s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_550] 1 True 20.43
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.484s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7919s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7952s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_616] 1 True 20.89
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.478s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8477s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8485s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8511s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_238] 1 True 11.21
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.353s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4329s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4347s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_72] 1 True 14.87
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5313s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_369] 1 True 19.79
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.468s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3689s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_260] 1 True 14.77
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.543s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7939s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8964s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8983s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_110] 1 True 18.43
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.36s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.595s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8684s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1702] 1 False 13.76
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.351s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4014s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4034s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_280] 1 True 13.04
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5840s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5854s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1204] 1 False 17.78
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.475s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6095s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6307s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6322s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_492] 1 True 12.13
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.350s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4353s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4526s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4549s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_229] 1 True 18.03
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.477s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5960s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5984s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_122] 1 True 20.84
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.301s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3614s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3629s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_207] 1 True 17.88
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.569s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9805s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9838s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_264] 1 True 12.19
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.590s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10169s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_432] 1 True 9.29
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.385s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4184s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4200s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_578] 1 True 21.29
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.329s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3875s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3886s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_426] 1 True 16.51
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8495s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8523s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_84] 1 True 21.45
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.294s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2040s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3236s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3249s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_21] 1 True 12.10
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9497s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9525s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_576] 1 True 18.17
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.394s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4407s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4424s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_16] 1 True 17.74
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.347s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3208s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3835s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1782] 1 False 9.81
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.330s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4007s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4022s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_46] 1 True 13.48
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.490s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8833s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8862s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_557] 1 True 10.01
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.460s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4905s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8284s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8315s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_586] 1 True 15.91
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9560s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9590s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_468] 1 True 10.73
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4995s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5011s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_327] 1 True 18.38
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5432s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.7306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.7440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10119s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10146s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_487] 1 True 13.04
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8985s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9014s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_531] 1 True 22.84
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.38s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_358] 1 True 14.40
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3016s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_470] 1 True 12.93
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.528s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6368s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7272s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7306s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_148] 1 True 12.36
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5434s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5452s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_618] 1 True 20.04
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5087s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7134s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8706s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8733s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_165] 1 True 15.49
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5763s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7492s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_75] 1 True 14.83
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.307s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2755s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4125s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_566] 1 True 16.94
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.276s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1799s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1876s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2505s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2521s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_189] 1 True 12.19
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.275s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2687s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3423s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3437s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_295] 1 True 21.38
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.286s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2014s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3044s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_63] 1 True 9.87
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4301s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4317s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1] 1 True 17.80
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.409s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3352s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4267s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4328s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4342s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_451] 1 True 12.49
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.527s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4405s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4993s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6554s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6581s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_504] 1 True 14.19
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.300s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2866s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2879s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 36302941 bytes MEM: Free's : 26 free's of 36302941 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_100] 1 True 11.88
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.289s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1918s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2874s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2883s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_600] 1 True 18.33
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.545s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3139s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3830s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3847s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 57791469 bytes MEM: Free's : 26 free's of 57791469 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_160] 1 True 10.38
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.465s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4505s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5651s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1026] 1 False 11.36
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.332s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2595s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3586s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3597s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_153] 1 True 11.42
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.296s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2588s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2972s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3219s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3233s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1073] 1 False 22.25
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.522s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8997s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9028s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_366] 1 True 19.57
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.511s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7615s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7641s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_462] 1 True 23.38
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.37s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.561s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3898s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6501s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9015s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9055s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_109] 1 True 16.03
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.319s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2976s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4143s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4159s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18673877 bytes MEM: Free's : 26 free's of 18673877 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_753] 1 True 18.18
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.356s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4947s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4963s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 29876173 bytes MEM: Free's : 26 free's of 29876173 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_512] 1 True 9.31
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4875s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5260s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5274s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_386] 1 True 22.77
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.346s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3076s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4163s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4180s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_510] 1 True 15.88
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.39s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.40s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.581s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5650s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8044s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8168s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10046s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10082s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_617] 1 True 9.43
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3647s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3663s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_202] 1 True 14.69
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.519s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4583s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6042s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6832s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7438s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7902s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7932s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_709] 1 True 18.20
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.449s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3538s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4248s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4478s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4493s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1170] 1 False 13.68
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.259s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2579s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3680s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3691s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_129] 1 True 17.52
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.533s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5214s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6880s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6983s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8839s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8872s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_605] 1 True 12.48
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.529s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8126s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8254s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9331s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9358s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_134] 1 True 22.58
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.396s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3215s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3487s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3690s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5453s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5598s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5661s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5680s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1299] 1 False 18.71
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.521s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5493s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6867s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9104s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9130s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_365] 1 True 10.00
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.30s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.605s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5885s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7299s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9600s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9625s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_45] 1 True 10.97
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.479s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4882s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6118s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6484s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6915s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7408s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7434s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_293] 1 True 14.56
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.473s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4646s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4887s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5397s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5523s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6657s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7097s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7454s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8589s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8604s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8626s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_562] 1 True 16.16
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6854s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7275s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8374s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_251] 1 True 19.04
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.493s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6637s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8308s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9110s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9142s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_396] 1 True 12.03
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.467s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6478s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8176s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8702s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_62] 1 True 16.49
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4534s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4969s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6068s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6203s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8399s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8430s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_526] 1 True 9.58
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.342s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2659s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2883s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2946s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3025s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3074s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3897s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3973s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3990s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_691] 1 True 20.22
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.524s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5635s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6236s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6624s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6776s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6796s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_587] 1 True 10.19
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.520s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5759s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6266s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6355s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6769s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8163s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8674s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8704s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_3] 1 True 22.79
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.551s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7038s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8295s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8824s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8849s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_389] 1 True 9.78
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.320s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2351s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2964s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3575s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3610s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3900s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4047s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4157s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_808] 1 True 18.33
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.557s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5616s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7309s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8116s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9113s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9136s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18699757 bytes MEM: Free's : 26 free's of 18699757 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1138] 1 False 19.54
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.313s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2698s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3770s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3784s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_18] 1 True 22.11
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.326s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3361s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3465s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3660s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5193s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6045s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6061s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657121 bytes MEM: Free's : 26 free's of 18657121 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_498] 1 True 10.65
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.445s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3222s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4187s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4317s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4656s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5010s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5326s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6003s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6023s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_923] 1 False 16.11
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw21] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.395s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4327s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4437s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4582s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5612s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6605s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6808s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6989s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7000s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_476] 1 True 19.91
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.494s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3603s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4942s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5003s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5527s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6626s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6647s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_441] 1 True 15.68
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.489s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4873s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4988s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5090s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6502s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9367s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9828s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9908s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10099s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10126s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_700] 1 True 17.09
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw11] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.297s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2747s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2850s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3815s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3927s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4130s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5025s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5036s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24859213 bytes MEM: Free's : 26 free's of 24859213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_547] 1 True 20.50
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.541s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5085s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5371s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5530s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5628s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6001s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6794s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9182s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9211s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_514] 1 True 17.13
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.510s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4835s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.6711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.6801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.7035s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.7135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.7199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.7307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.8186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.8472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.9050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.9156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.9233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.9304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9420s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9809s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.10016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.10086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.10164s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10396s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10607s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10899s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10919s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_372] 1 True 10.35
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.536s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4950s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5290s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6100s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6447s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7027s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9120s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9684s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9710s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_15] 1 True 12.20
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.945s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5940s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6079s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.10000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10209s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10403s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10779s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10810s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671737 bytes MEM: Free's : 26 free's of 18671737 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_613] 1 True 14.09
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.425s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2511s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2893s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2947s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3149s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3606s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3733s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4626s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4997s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5700s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5782s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5809s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_200] 1 True 20.73
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.28s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.31s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.1612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4941s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5306s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5722s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6235s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7202s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7524s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8153s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8549s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8737s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8765s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_524] 1 True 21.56
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw6] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.277s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1796s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2041s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2386s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2639s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2731s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2757s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2810s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2894s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2901s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_461] 1 True 16.77
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.488s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3272s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3714s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3909s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4532s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5109s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5171s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5388s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5448s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5597s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5751s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5836s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6426s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6450s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1916] 1 False 15.05
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.483s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4676s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6365s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8263s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8497s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10247s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10255s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23245933 bytes MEM: Free's : 26 free's of 23245933 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_290] 1 True 9.35
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.315s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2376s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2841s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3146s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3175s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3585s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3631s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3788s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3817s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4136s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4147s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20587213 bytes MEM: Free's : 26 free's of 20587213 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_65] 1 True 17.71
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.400s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1658s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1673s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1877s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2091s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2107s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2300s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2343s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2382s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2400s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2405s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1260] 1 False 16.89
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.266s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1426s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1625s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1775s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2470s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2565s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2618s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2675s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2699s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2843s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2952s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2980s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3049s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3062s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 20266093 bytes MEM: Free's : 26 free's of 20266093 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_513] 1 True 12.91
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.446s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5567s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5708s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5750s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6124s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6219s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6468s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6842s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6996s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7419s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7552s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7664s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8342s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8572s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8594s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_145] 1 True 12.69
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.547s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4541s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5340s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6938s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7211s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7297s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7868s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7965s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8134s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8161s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18692813 bytes MEM: Free's : 26 free's of 18692813 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_317] 1 True 22.65
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.328s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2113s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2165s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2604s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2795s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2961s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3161s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3332s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3418s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3608s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3718s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3786s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3798s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 25089741 bytes MEM: Free's : 26 free's of 25089741 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_353] 1 True 10.15
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.612s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5677s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6385s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6999s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.7293s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7526s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7622s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7814s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8425s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8614s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8797s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9398s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9482s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9716s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9744s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_522] 1 True 19.56
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4802s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5226s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5318s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5716s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6553s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7246s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7410s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7895s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8212s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8438s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8465s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_380] 1 True 18.59
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw1] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.292s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3268s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3596s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3869s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4008s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4031s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4200s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4227s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4258s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4383s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4417s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4544s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4683s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4729s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4829s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4840s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_503] 1 True 20.20
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3851s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4727s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4884s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4949s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5282s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5834s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6320s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6446s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6879s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6899s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 39770053 bytes MEM: Free's : 26 free's of 39770053 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_439] 1 True 15.09
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3441s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3496s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3744s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4070s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4125s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4283s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4348s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4578s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5119s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5180s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5387s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5641s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5832s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5851s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 38576237 bytes MEM: Free's : 26 free's of 38576237 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_391] 1 True 15.95
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.268s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2288s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2466s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2510s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2568s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2642s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2665s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2743s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2819s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2896s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3022s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3037s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3098s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3102s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3112s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_354] 1 True 18.42
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw9] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.14s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.359s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2963s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3089s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3244s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3407s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3586s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3770s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3866s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4062s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4104s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4346s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4485s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4690s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4706s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 24899693 bytes MEM: Free's : 26 free's of 24899693 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_188] 1 True 20.87
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.20s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.499s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4331s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4685s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4962s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5123s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5486s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5645s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5925s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6242s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6310s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6393s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6602s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6760s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6920s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7229s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7321s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7492s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7748s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7756s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7778s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_114] 1 True 20.02
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.48s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.52s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.666s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4434s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4525s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5633s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6069s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6158s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6337s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6464s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6561s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6886s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6986s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7191s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7362s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8147s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8444s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8573s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8697s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8971s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9239s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9272s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_173] 1 True 19.04
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.27s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.562s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4679s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5162s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5377s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5459s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5512s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5569s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5644s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6050s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6108s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6169s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7023s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7563s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7846s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8284s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8502s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8537s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_664] 1 True 12.37
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw17] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.290s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1735s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1829s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2005s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2045s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2228s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2253s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2335s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2421s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2458s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2681s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2742s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2845s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2872s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2957s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3051s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3177s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3217s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3261s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3265s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3279s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19834621 bytes MEM: Free's : 26 free's of 19834621 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_85] 1 True 12.94
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.22s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.25s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.452s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3973s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5172s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5240s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5291s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5480s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5778s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6015s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6075s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6128s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6199s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6401s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6566s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6598s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18671317 bytes MEM: Free's : 26 free's of 18671317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_95] 1 True 9.37
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.317s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2680s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2791s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2822s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2857s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2922s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2985s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4428s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4601s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4901s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5002s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5049s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5233s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5329s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5354s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5445s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.5488s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.5535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5706s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5712s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5728s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18656749 bytes MEM: Free's : 26 free's of 18656749 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_171] 1 True 13.09
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw22] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.492s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3131s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3390s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3611s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3858s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4213s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4364s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4433s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4666s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4720s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4776s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4954s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5056s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5204s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5303s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5370s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5435s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5640s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.5773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.5825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.5878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.5960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6102s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6415s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_248] 1 True 9.46
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw18] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.12s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.325s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2132s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2276s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2414s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2475s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2522s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2623s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2982s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3156s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3197s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3232s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3357s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3395s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3562s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3705s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3736s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3779s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3974s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4030s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4137s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4192s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4243s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4288s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4302s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_54] 1 True 17.74
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw0] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.24s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.457s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.3424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3649s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4078s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.4140s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.4210s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.4260s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.4440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.4682s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.4764s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.4826s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.4928s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5006s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5081s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5189s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.5328s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.5412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.5473s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.5540s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.5629s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.5704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.5793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.5889s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.5989s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.6067s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.6159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.6271s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.6344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.6452s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.6574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.6643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.6734s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.6833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.6919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.6929s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.6949s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_555] 1 True 17.91
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw14] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.17s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.503s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4636s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4977s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5289s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5422s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5516s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5732s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5792s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5848s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6077s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6251s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6311s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6415s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6560s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6724s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.6789s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.6888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.6968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7173s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7256s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7442s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7554s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7844s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.7935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.7946s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.7969s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_548] 1 True 13.46
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw7] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.18s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.383s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2304s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2345s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2391s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2499s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2528s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2593s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2627s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2678s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2712s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2805s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2849s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2910s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2981s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3013s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3052s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3122s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3330s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3380s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3413s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3467s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3536s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3564s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3600s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3638s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3821s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3859s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3903s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3914s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 35977885 bytes MEM: Free's : 26 free's of 35977885 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_894] 1 False 16.04
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw19] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------ | Node | Node Name | Reason | ------------------------------------------------------------------------------------ | Unsqueeze | output | Output dimensions after unsqueeze must be less than <= 6 | ------------------------------------------------------------------------------------ ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.19s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.573s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5080s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5190s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5262s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5479s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5711s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6032s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6106s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6294s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6520s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7159s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7356s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7490s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7574s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7693s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7773s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7870s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8178s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8307s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8408s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9278s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9306s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9338s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18954349 bytes MEM: Free's : 26 free's of 18954349 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_472] 1 True 13.91
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.753s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4533s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4878s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4966s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5339s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5507s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5576s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5781s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5933s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6028s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6141s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6255s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6451s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.6584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.6670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.6772s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.6906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.6998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7186s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7336s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.7431s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.7504s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7670s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7746s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7987s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8043s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.8223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.8287s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.8378s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.8449s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8513s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8516s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8540s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65810305 bytes MEM: Free's : 26 free's of 65810305 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_169] 1 True 14.18
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw20] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.29s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.32s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.532s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5220s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5296s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5543s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5839s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.6423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.6500s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.7250s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7471s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7951s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8065s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.8277s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.8427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8515s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8599s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8688s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8783s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9274s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9384s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.9457s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.9558s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9804s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9894s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10141s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10172s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18702445 bytes MEM: Free's : 26 free's of 18702445 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1700] 1 False 19.85
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.21s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.440s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4183s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4375s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4730s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.4959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5009s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5092s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5201s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5360s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5409s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.5550s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.5613s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.5689s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.5762s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.5820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.5899s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.6547s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.6661s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.6745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.6824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.6881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.6978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.7048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.7110s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.7207s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.7264s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.7325s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.7439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.7506s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.7577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.7692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.7758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.7813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.7937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.8016s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.8024s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.8045s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 23854573 bytes MEM: Free's : 26 free's of 23854573 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_1065] 1 False 20.48
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw16] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 1 | 1 | | CPU | 1 | x | ------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- | Node | Node Name | Reason | ------------------------------------------------------------------------------------------------------- | Unsqueeze | output | Layer 1 - op type Unsqueeze, Unknown input dimension, not supported by TIDL | ------------------------------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.327s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2816s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3063s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3142s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3194s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3286s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3333s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3494s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3542s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3587s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3771s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3855s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3907s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4004s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4055s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4099s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4381s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4424s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4529s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4577s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4621s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4667s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4707s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4912s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5029s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5033s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5039s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= Warning : Couldn't find corresponding ioBuf tensor for onnx tensor with matching name -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18657325 bytes MEM: Free's : 26 free's of 18657325 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_601] 1 True 17.95
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw4] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.15s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.16s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.464s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.4363s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.4580s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.4654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.4737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.4825s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.4911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.4995s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.5073s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.5167s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.5231s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.5334s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.5474s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.5551s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.5652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.5721s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.5798s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.6991s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.7195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.7280s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.7399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.7489s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.7590s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.7671s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.7738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.7812s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.7926s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.8021s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.8096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.8160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.8241s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.8519s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.8668s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.8737s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.8806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.8874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.8960s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.9066s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.9154s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.9237s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.9315s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.9412s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.9418s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.9441s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 65493245 bytes MEM: Free's : 26 free's of 65493245 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_234] 1 True 13.43
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw12] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.23s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.26s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.540s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.5083s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.5430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.5518s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.5594s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.5725s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.5831s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.5979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.6058s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.6135s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.6239s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.6316s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.6456s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.6555s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.6709s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.7861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.8143s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.8257s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.8347s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.8455s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.8559s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.8653s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.8786s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.8863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.8937s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.9033s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.9112s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.9181s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.9298s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.9366s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.9443s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.9572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.9692s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.9806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.9919s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.10018s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.10088s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.10225s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.10319s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.10394s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.10537s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.10634s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.10651s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.10685s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19374189 bytes MEM: Free's : 26 free's of 19374189 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_212] 1 True 15.91
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw5] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.10s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.331s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2704s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2777s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2862s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2931s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2998s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3157s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3205s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3270s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3323s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3427s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3481s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3546s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3592s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3652s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3703s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3756s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.3807s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.3865s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3924s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4057s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4111s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4174s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4223s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4402s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4508s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4570s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4684s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4740s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4793s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4852s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4917s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4967s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.5019s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.5084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.5145s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.5149s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.5160s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 19519181 bytes MEM: Free's : 26 free's of 19519181 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_393] 1 True 10.55
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw10] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.237s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2404s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2440s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2460s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2491s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2517s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2535s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2556s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2571s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2591s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2609s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2643s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2663s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2696s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2767s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2833s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2856s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2874s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2914s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2929s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2955s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2975s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2992s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3039s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3064s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3082s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3114s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.3182s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.3198s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.3216s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.3245s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.3274s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.3280s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 26142413 bytes MEM: Free's : 26 free's of 26142413 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_53] 1 True 13.14
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw8] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.7s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.197s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.1701s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.1745s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.1800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.1838s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.1879s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.1916s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.1953s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.1984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2121s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2148s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2188s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2218s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2252s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2285s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2341s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2372s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.2406s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.2439s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.2469s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.2498s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.2566s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.2615s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.2632s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.2648s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.2662s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.2672s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.2686s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.2702s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.2717s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.2728s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.2741s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.2753s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.2768s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.2780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.2790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.2806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.2818s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.2819s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.2822s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18672013 bytes MEM: Free's : 26 free's of 18672013 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_147] 1 True 10.91
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw13] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.8s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.9s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.158s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2195s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.2265s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.2305s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.2344s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.2389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.2430s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.2476s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.2514s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.2548s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.2584s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.2620s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.2669s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.2710s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.2749s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.2785s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.2827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.2863s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.2903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.2936s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.2978s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.3020s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.3060s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.3094s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.3133s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.3170s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.3221s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.3259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.3301s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.3338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.3373s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.3416s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.3463s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.3503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.3545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.3581s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.3617s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4630s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4782s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4803s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4824s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4826s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4830s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18674797 bytes MEM: Free's : 26 free's of 18674797 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_107] 1 True 10.57
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw15] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.104s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.891s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.906s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.921s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.934s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.945s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.956s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.1184s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.1196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.1206s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.1224s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.1234s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.1249s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.1259s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.1269s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.1279s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.1292s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.1302s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.1314s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.1324s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.1338s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.1349s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.1359s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.1369s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1379s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1389s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1400s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1411s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1423s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1436s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1450s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1462s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1472s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1483s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1495s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1509s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1521s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1531s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1545s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1557s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1557s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1559s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18659005 bytes MEM: Free's : 26 free's of 18659005 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_416] 1 True 9.63
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw3] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.113s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.674s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.691s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.713s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.723s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.739s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.752s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.765s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.774s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.787s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.801s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.811s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.827s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.853s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.864s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.892s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.903s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.913s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.932s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.943s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.958s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.984s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.994s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.1007s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1017s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1026s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1036s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1048s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1059s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1072s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1086s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1103s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1115s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1129s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1144s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1155s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1166s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1179s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1180s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1184s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 42522317 bytes MEM: Free's : 26 free's of 42522317 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_543] 1 True 7.64
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw2] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 4 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.11s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.13s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.312s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.2944s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.3054s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.3101s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.3138s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.3185s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.3230s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.3273s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.3312s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.3350s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.3399s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.3654s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.3719s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.3758s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.3806s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.3840s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.3888s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.3930s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.3968s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.4012s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.4053s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.4096s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.4151s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.4196s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.4238s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.4281s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.4322s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.4358s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.4392s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.4429s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.4461s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.4503s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.4539s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.4572s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.4619s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.4655s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.4695s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.4738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.4784s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.4820s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.4860s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.4904s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.4907s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.4915s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 33156829 bytes MEM: Free's : 26 free's of 33156829 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!
Passed test_tidl_unit.py::test_tidl_unit_operator[Unsqueeze_198] 1 True 4.22
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3[gw23] linux -- Python 3.10.16 /home/tidl/.pyenv/versions/benchmark/bin/python3
------------------------------Captured stdout call------------------------------
========================= [Model Compilation Started] ========================= Model compilation will perform the following stages: 1. Parsing 2. Graph Optimization 3. Quantization & Calibration 4. Memory Planning ============================== [Version Summary] ============================== ------------------------------------------------------------------------------- | TIDL Tools Version | 11_00_00_00 | ------------------------------------------------------------------------------- | C7x Firmware Version | 11_00_00_00 | ------------------------------------------------------------------------------- | Runtime Version | 1.15.0 | ------------------------------------------------------------------------------- | Model Opset Version | 19 | ------------------------------------------------------------------------------- ============================== [Parsing Started] ============================== [TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options ------------------------- Subgraph Information Summary ------------------------- ------------------------------------------------------------------------------- | Core | No. of Nodes | Number of Subgraphs | ------------------------------------------------------------------------------- | C7x | 2 | 1 | | CPU | 0 | x | ------------------------------------------------------------------------------- ============================= [Parsing Completed] ============================= ==================== [Optimization for subgraph_0 Started] ==================== ----------------------------- Optimization Summary ----------------------------- ---------------------------------------------------------------------------- | Layer | Nodes before optimization | Nodes after optimization | ---------------------------------------------------------------------------- | TIDL_LogLayer | 1 | 0 | | TIDL_EltWiseLayer | 1 | 0 | ---------------------------------------------------------------------------- Total nodes in subgraph: 5 =================== [Optimization for subgraph_0 Completed] =================== The soft limit is 10240 The hard limit is 10240 MEM: Init ... !!! MEM: Init ... Done !!! 0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO 0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR 0.4s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING 0.75s: VX_ZONE_INFO: [ownAddTargetKernelInternal:189] registered kernel vx_tutorial_graph.phase_rgb on target DSP-1 0.694s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0 0.715s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1 0.726s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2 0.738s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3 0.754s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1 0.766s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_2 0.780s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_3 0.790s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_4 0.800s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_5 0.813s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_6 0.823s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_7 0.837s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP_C7-1_PRI_8 0.847s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSP-1 0.861s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-0 0.871s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_NF 0.881s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_LDC1 0.890s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC1 0.902s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_MSC2 0.911s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_VISS1 0.923s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE1 0.935s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE2 0.948s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE3 0.959s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE4 0.970s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE5 0.979s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE6 0.990s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE7 0.1000s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CAPTURE8 0.1011s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY1 0.1024s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DISPLAY2 0.1034s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX 0.1046s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target CSITX2 0.1061s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M1 0.1071s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M2 0.1084s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M3 0.1093s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DSS_M2M4 0.1105s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target VPAC_FC 0.1117s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU2-1 0.1127s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_SDE 0.1136s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target DMPAC_DOF 0.1150s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-0 0.1160s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MCU3-1 0.1161s: VX_ZONE_INFO: [tivxInit:152] Initialization Done !!! 0.1163s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO ============= [Quantization & Calibration for subgraph_0 Started] ============= -------- Running Calibration in Float Mode to Collect Tensor Statistics -------- [=============================================================================] 100 % ------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------ [=============================================================================] 100 % ==================== [Quantization & Calibration Completed] ==================== [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. Rerunning network compiler... [TIDL Import] WARNING: Couldn't open perfSimTool file: /home/tidl/pranav/edgeai-benchmark/tools/tidl_tools_package/AM68A/tidl_tools/ti_cnnperfsim.out. Skipping Performance Simulation. [TIDL Import] [PARSER] WARNING: ******************************************************************** * Network compiler returned with error or didn't executed * * This model can only be used on PC/Host emulation mode * * It is not expected to work on target/EVM * ******************************************************************** ======================== Subgraph Compiled Successfully ======================== MEM: Deinit ... !!! MEM: Alloc's: 26 alloc's of 18724557 bytes MEM: Free's : 26 free's of 18724557 bytes MEM: Open's : 0 allocs of 0 bytes MEM: Deinit ... Done !!!